VMEbus FAQ's
"Frequently Asked Questions for the Beginning VMEbus User"By John Rynearson, Technical Director, VITA
Question: What factors differentiate backplane buses? Aren't all buses basically the same?
While all backplane buses are based on the concept of using a shared resource, there are several fundamental attributes that differentiate one backplane bus architecture from another. These attributes include: multiplexed address and data signals versus non multiplexed address and data signals, asynchronous versus synchronous operation, mechanicals, connector type, number of module slots, addressing and data width, and single versus multi-master capability. Let's take a look at each of these attributes.
Multiplexed versus Nonmultiplexed- One common difference between buses is multiplexed versus nonmultiplexed address and data lines. Multiplexing allows a single set of lines to be used for addresses during one part of the bus cycle and for data during the other part. Multiplexing address and data on a single set of lines reduces the number of interconnects needed to support the bus, but requires additional logic to support multiplexing. For example, to handle 64 address and data lines only 64 interconnects are required.
The alternative to multiplexing lines is to have individual lines for both address and data. For 32 bits of address and data, 64 lines are required. One advantage is that no multiplexing logic is required on the address and data lines.
The VMEbus is a 32 bit nonmultiplexed bus and a 64 bit multiplexed bus. The fact that VME was initially nonmultiplexed allowed it to expand to 64 bit capability in an interoperable manner later on.
Asynchronous versus Synchronous Clocking- Another important attribute in bus operation is signal timing. A synchronous bus is driven by a common clock and all signals are sampled based on the common clock. An asynchronous bus does not provide a common timing clock. Instead events that occur are acknowledged with a handshake signal. Synchronous buses are considered to be more immune to noise, since lines are sampled only when the clock occurs. Because the timing is driven by a known clock, bus noise that occurs at other times is ignored. Unfortunately, the data rate for a synchronous bus must be fixed at a specific value. As technology improves and provides shorter gate delays, the speed of the synchronous bus remains the same. It's performance cannot improve with improvements in technology. An asynchronous bus does not use a common clock. Data transfers between boards take place at the fastest rate at which acknowledgments can take place. As technology improves, the rate of asynchronous transfers increases.
Bus Mechanics- While much attention is given to the electrical nature of a bus, the mechanics are of equal importance. The interconnect between the module and the backplane is key to good reliability. Most buses today use some style of pin and socket interconnect. Card edge interconnects which used plated surfaces on the printer circuit board were common in the 1970's. However, they do not have the reliability needed by today's real-time embedded applications.
Many embedded applications exist in environments that require robust mechanics. The packaging must provide a means for handling cabling and insuring that modules are seated firmly. Cooling is another important aspect of mechanicals. The VMEbus uses a packaging standard that originated in Europe in the late 1970's and is known as the Euroboard or Eurocard standard. Besides mandating a pin and socket connector it provides for front panels, standard board sizes, card guides, chassis, and panel racks that meet the needs for embedded real-time applications.
Slots, slots, and more slots- One important attribute of a backplane bus architecture is the number of modules that can be plugged into the backplane. Most embedded real-time applications require expandability. The number of slots in a backplane architecture depend on the capability of the logic driving the backplane. The VMEbus uses high current TTL drivers and receivers and provides for a maximum of 21 slots on 0.8 inch spacing. This maximum configuration fits nicely into a 19 inch panel rack.
Address and Data Bus Width- Bus architectures have evolved with microprocessors. Early bus architectures provided 16 bit address buses and 8 bit data buses. Later microprocessor architectures have pushed the address bus from 16 bits, to 24 bits, 32 bits, and now 64 bits. Similarly the data bus has evolved from 8 bits, to 16 bits, to 32 bits, and now 64 bits. The VMEbus although it was first introduced in the early 1980's provides data transfers from 8 to 64 bits and addresses from 16 to 64 bits. The ability to handle a range of address and data widths provides flexibility. VME modules span the range from single function slave boards for simple I/O requirements to complex multifunction computer modules with sophisticated on-board I/O.
Single Master versus Multi-Master- The bus is a shared resource. Some bus architectures allow only one module to control the bus. All transfers must be arranged and coordinated through a single master. The VMEbus uses a multimaster architecture. Any module with master capability can control the bus. A multimaster architecture supports concurrent operation, is more powerful, and provides more flexibility.
Summary- Not all bus architectures are the same. Important fundamental attributes provide key differentiaters. When selecting a bus architecture for your next project make sure these fundamental attributes match both your short term and long term needs.