The VME family of specifications has grown significantly since its inception. VMEbus has expanded from the original family of a core VME32 parallel bus specification, a VME Subsystem bus, and a VME serial interconnect to today's broad family of complementary state-of-the art specifications.
As the serial switch fabric solutions that include Ethernet, PCI Express, RapidIO, Infiniband and other alternatives gain popularity and additional usage to form critical mass in the industry, specific purpose parallel and serial subsystem buses will start sharing market space by solving different problems within tomorrow's embedded systems. VITA is evolving to incorporate the appropriate alternatives.
VITA Technology includes several mezzanine specifications that have been optimized for use in critical embedded system environments. Low profile, small form factor mezzanine solutions of various types have been developed with several obtaining ANSI approval. IP modules, M-modules, PC*MIP, FMC, and the very popular PMC modules all work effectively in critical embedded system applications, evolving as technology and application needs change.
Several system management and support specifications have also been ratified that make the development of systems easier with more robust system management. Proposals continue to be submitted and considered for addition to the VITA Technology family to improve utilization in complex systems.
VITA is also involved in activities to enhance reliability prediction and certification standards as it relates to electronic modules. The Reliability Prediction Community is leading the efforts to improve the tools available to designers.
The specifications database has a complete listing of the many specifications along with their current status.
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|ANSI/VITA 1.0-1994 (S2011)||VME64||The VME64 specification establishes a framework for 8-, 16-, 32, and 64-bit parallel-bus computer architectures that can implement single and multiprocessor systems. This bus includes the initial four basic sub-buses: (1) data transfer bus, (2) priority interrupt bus, (3) arbitration bus, and (4) utility bus. The data transfer bus supports 8-, 16-, 32-, and 64-bit data transfers in multiplexed and non multiplexed form. The transfer protocols are asynchronous with varying degrees of handshaking dependent on the speeds required. The priority interrupt subsystem provides real-time interrupt services to the system. The allocation of bus mastership is performed by the arbitration subsystem which allows the implementation of several prioritization algorithms. The utility bus provides the system with power plus power-up and power-down synchronization. The mechanical specifications of boards, backplanes, subracks, and enclosures are based on IEC 297 and IEEE 1101.1 specifications, also known as the Eurocard form factor. Additional standards exist that can be used as sub-busses to this architecture for data transfer transactions, peripheral interfaces and intra-crate communications among compatible modules.||ANSI Stabilized|
|ANSI/VITA 1.1-1997 (S2011)||VME64x Extensions||This specification is an extension of the ANSI/VITA 1-1994, VME64 specification. It defines a set of features that can be added to VME32 and VME64 boards, backplanes and subracks. These features include a 160 pin connector, a P0 connector, geographical addressing, voltages pins for 3.3V, a test and maintenance bus, and EMI, ESD, and front panel keying per IEEE 1101.10.||ANSI Stabilized|
|ANSI/VITA 1.3-1997 (S2011)||VME64x 9U x 400 mm Format||This specification is an extension of the ANSI/VITA 1-1994, VME64 specification. It defines 9U x 400 mm boards, backplanes and subracks.
The VME64x specification expands the features of VME64 mainly by using a different 160 pin connector. These and other features in the VME64x standard gained the interest of the Telecommunications Industry and the Physics Research Community. A major concern in both groups was a larger board format yet keeping as much compatibility with the existing VME standards as possible. This standard is a response to these needs.
|ANSI/VITA 1.5-2003 (R2009)||VME 2eSST||This specification is an extension of the ANSI/VITA 1-1994, VME64 and ANSI/VITA1.1-1997, VME64x specifications. It defines a transfer protocol, based upon source synchronous concepts, that permits the VMEbus to operate at rates to at least 320MB/s. As technology improves, this rate can be extended to higher levels.
The 2eSST protocol requires low skew between signals and monotonic rising and falling edges on the signals. To meet these requirements, limited length backplanes, special backplane topologies and/or enhanced transceivers are required. The specification calls for enhanced bus transceivers with controlled rise and fall times, tightly defined thresholds, low part to part skew and LVTTL levels. During the development of this standard, specific transceivers were developed to meet these requirements.
|ANSI/VITA 1.6-2000 (S2011)||Keying for Conduction-cooled VME64x||This specification is an extension of the ANSI/VITA 1.1-1997, VME64x specification. It defines an alternate keying system that can be added to VME64x boards and backplanes in a conduction cooled environment (IEEE 1101.2) where keying as defined in the VME64 Extensions standard cannot be applied.||ANSI Stabilized|
|ANSI/VITA 1.7-2003 (R2009)||Increased Connector Current Level||The P1/J1 and P2/J2 current rating limits of the 3 row DIN and 5 row DIN connector pins listed in the DIN41612, IEC 603-2 and 61076-4-113 specifications are based on full loading of the connector. In VME, VME64, and VME64 Extensions applications, the power pins represent only a small fraction of the total number of pins and are spread throughout the connector. The remaining pins are used to carry electrical signals, which add a negligible heating contribution. The net effect is that the connector heating is less, which allows a higher current carrying capacity.
Power contacts of connectors tested and certified in accordance with this standard are capable of passing 2.0 amps per contact on a selected group of pins. The standard has been verified by testing connectors from multiple vendors and it has been developed and approved by a broad cross-section of the VMEbus community.
|ANSI/VITA 3-1995 (S2011)||Board Level Live Insertion||This specification identifies methodologies through which a faulty board can be removed from a system and a replacement board can be inserted while the system continues to operate. The primary motivation for supporting Board Level Live Insertion within the VMEbus environment is to enhance the current VMEbus standard while maximizing the use of existing off-the-shelf VMEbus products.||ANSI Stabilized|
|ANSI/VITA 4.0-1995 (S2011)||IP Modules||This specification defines a versatile module, known as an "IP module." These modules provide a convenient method of implementing a wide range of I/O, control, interface, slave processor, analog and digital functions. IP modules, about the size of a traditional business card, mount parallel with a host Carrier board, which provides host processor or primary bus interfacing, as well as mechanical means for connecting the IP module's I/O to the outside world. Typical Carriers include standalone processors, DSP based carriers, as well as desktop buses and VME based boards. This specification includes mechanical, host bus electrical, and logical definition of I/O space, memory space, identification space, interrupts, DMA, and reset functions. Two physical sizes, two fixed clock rates, and multiple data width sizes to 32-bits are defined.||ANSI Stabilized|
|ANSI/VITA 4.1-1996 (S2011)||IP I/O Mapping to VME64x||With the development of the VME64x, 205 user defined I/O pin are available for rear backplane I/O. It is practical to route multiple IP's I/O through the VME64x backplanes. This standard defines the mapping of the 50 user defined I/O pins from the IP module (ANSI/VITA 4-1995 (R2002)) I/O connectors to VME64x board's rear I/O connectors in a consistent method across all VME64x boards, backplanes and rear I/O transition boards.||ANSI Stabilized|
|ANSI/VITA 5.1-1999 (S2011)||RACEway Interlink on VME||This specification provides a definition of the data link protocol and physical interface of a high performance extension to the VMEbus specification. This extension consists of high bandwidth, low latency interconnects across a VMEbus computer chassis backplane using the P2 connector. Bi-directional connectivity between boards in a VMEbus chassis is achieved through the use of a network of crossbar switches with point-to-point interconnects. RACEway Interlink is a VMEbus enhancement that can deliver up to 3.2 Gbytes/sec of scalable bandwidth over rows A, C, D and Z of the P2 connector in a standard VMEbus chassis. In addition to increased bandwidth, RACEway Interlink offers: 1) low latency, deterministic transactions, 2) concurrent point-to-point transactions for multiple simultaneous transfers, and 3) scalable bandwidth so total bandwidth increases as more slots are added. Many new applications, especially those with multiple processors and multiple real-time I/O interconnects, require these capabilities.||ANSI Stabilized|
|ANSI/VITA 6.0-1994 (S2011)||Signal Computing System Architecture (SCSA) on VME||The Signal Computing System Architecture (SCSA) specification establishes a framework for the inter- and intra-system transfer of serial media data and control information oriented toward the development of high density call and voice processing products and systems. The SCSA architecture is application specific and is embodied as a family of buses that are defined in this physical layer of the specification to reside on the VMEbus J2/P2 connector. The SCSA buses coexist with products compliant with ANSI/VITA 1-1994, VME64. SCSA at the physical level consists of two separate subbuses, a sixteen line, TDM data transfer bus called the SCbus, and a serial, peer-to-peer communication link called the SCmessage bus. The primary purpose of the SCbus is to support the exchange of real time telephonic voice, facsimile, data, video and other media streams. The purpose of the SCmessage bus is to transport interprocess control and status messages. This specification defines only the physical and data link OSI layers of the eventual four layer transport facility.
The SC data transport bus is a synchronous, byte-serial, continuously framed bus organized as 16 serial data paths each divided into 32, 64, or 128 eight bit timeslots with a frame rate of 8,000 per second in order to accommodate intra-system telephonic voice and data transfers. The message bus is an HDLC framed, 2 Mbps, CSMA/CD packet bus that is bit-synchronized with the data transport bus. This specification covers the hardware specific elements of the VME-SCSA subbus including the message bus OSI protocol layers 1 and 2. Subsequent specifications provide an interface definition for the device specific software layer that provides compatibility between compliant VME-SCSA products and available upper layer SCSA resource management application programming interface(api) and other application software.
|ANSI/VITA 6.1-1996 (S2011)||SCSA Extensions||Addition of SCSA extensions to ANSI/VITA 6.0.||ANSI Stabilized|
|ANSI/VITA 10-1995||SKYchannel Packet Bus on VME||This specification describes a high performance SKYchannel Packet Bus architecture that is fully compatible with the VMEbus standards. This standard addresses communication between VME boards using the P2 connector. This includes the physical layer for communication between the VME board and a SKYchannel Backplane through VME P2/J2, and the data link layer for communication from board to board.
This specification does not address the physical layer for running SKYchannel within a SKYchannel Backplane or group of Backplanes, which is considered an implementation detail. The specification includes specifics of the packet protocol, signals, waveforms, timing diagrams and mechanical specifications.
|ANSI/VITA 12-1997 (S2012)||M-Module||This specification defines minimum mechanical and electrical characteristics of M-Modules, a method of implementing modular circuit boards with specific functions that can be used to add functionality to other larger printed circuit boards.
For special requirements, a third row can be added to the base board connection. This is described in the mechanical specification. The use of the additional signals or extended use of existing signals (in compliance with the basic electrical specification) can be standardized to a certain extent. Therefore, certain signals and signal groups are defined in the extended electrical specification as regards their function, timing and electrical characteristics. Modules complying with these additional specifications are designated MA-Modules.
|ANSI/VITA 17.0-1998 (S2011)||Front Panel Data Port (FPDP)||This extension to the VME specification consists of a multi-drop synchronous parallel non-addressable bus connection between multiple boards in a single chassis. The connection is made to a connector on the front panel of each board by means of an eighty conductor ribbon cable. The purpose of this specification is to allow products to be designed to work with other FPDP products. The degree of interoperability may depend on the layers of functionality above the physical and data link layers. These higher layers are not part of this specification.||ANSI Stabilized|
|ANSI/VITA 17.1-2003 (R2009)||Serial Front Panel Data Port||As the name implies, it is directly related to the Front Panel Data Port (FPDP) specification, deriving its serial protocol from the defined protocol and control signals of FPDP. This Serial FPDP specification supports three link speeds: 1.0625 Gbaud, 2.125 Gbaud, and 2.5 Gbaud. These three link speeds can support data transfer rates in excess of 105 MBps, 210 MBps, and 247 MBps respectively. Included in this definition are the data frame structure, the link layer protocol, and the physical media requirements.
The purpose of this specification is to allow products to be designed to work with other Serial FPDP products. The degree of interoperability will depend on the specific options implemented. Although all options are supported by this standard, not all products are required to support all options.
|VITA 17.2||Serial Front Panel Data Port (SFPDP) Channel Bonded Protocol||The main objective of VITA 17.2 is to increase the bandwidth of the link. This can be done by both increasing the speed of the link, and by providing the ability to channel bonding several lanes together.
The VITA 17.2 protocol is designed to provide functional compatibility with both VITA 17 and VITA 17.1 protocols, while providing increased bandwidth. In addition, the VITA 17.2 protocol is designed to provide a minimum footprint, and to maximize the use of dedicated hardware that is found in current FPGAs.
|Working Group - Draft|
|ANSI/VITA 20-2001 (R2011)||Conduction Cooled PMC||This specification defines the methodology and implementation details to allow the creation of conduction cooled PMC modules to ensure electrical and physical compatibility with various host card modules onto which conduction cooled PMCs are mounted.
The goal of this specification is to allow the intermixing of different vendors air and conduction cooled PMC modules onto air and/or conduction cooled host card modules to the maximum extent possible. Intermixing of air cooled PMC and conduction cooled PMC mezzanine modules on a single type of base/host card is generally intended for development purposes only.
|ANSI/VITA 23-1998 (S2011)||VME64 Extensions for Physics and Other Applications||This document is intended to be used internationally in physics applications and in other fields with similar requirements. It provides implementation rules, recommendations, and guidelines that enhance the use of the VMEbus standard as specified in ANSI/VITA 1-1994, VME and ANSI/VITA 1.1, VME64 Extensions. The VMEbus standards are the basis for this document. Hardware and software produced according to this document are in full compliance with the VMEbus standards. The Rules, Recommendations, Observations, etc. in this document are complementary to and compliant with existing VME standards. The Rules in this document are based on either Rules, Recommendations or Suggestions in a VME standard or draft standard as well as items not addressed by VME standards. This document is generally consistent with the NIM/VME-P document 9612, "VMEbus for Physics Applications", that has served as a working group approach, and has also utilized items from the CERN VSC "Recommended Practices" document.||ANSI Stabilized|
|ANSI/VITA 26-1998 (S2011)||Myrinet on VME Protocol||This specification describes the high-performance, inter-computer, Myrinet packet network that is fully compatible with existing VMEbus specification and their extensions. This specification addresses communication between VME boards using interconnect either on the front panel or on the backplane. The communication may use cables or an overlay (such as a backplane). The specification defines the interface between a VME board and Myrinet, allowing not only intra-subrack, board-to-board communication, but also a uniform extension for inter-subrack, inter-cabinet, and even local-area-network (LAN) communication. This standard includes, either directly or by reference, the specification of the Data Link level, timing information, character set, signals, and the details of the connectors.||ANSI Stabilized|
|ANSI/VITA 29.0-2001||PC*MIP||This specification defines the mechanical form factor and the pin assignments for a small form factor mezzanine module based on the PCI bus.||ANSI Withdrawn|
|ANSI/VITA 30.0-2000 (S2011)||2mm Connector Practice for Eurocard Systems||This document defines an equipment practice based on a combination of 2 mm connectors, per IEC 61076-4-101, and subracks, racks and printed boards based on the Euroboard form factors.
In the late 1980's, the VME specification expanded for 64 bit data and address capability, which also affected the specified connectors used at the plug-in module interface. The designers utilized IEC 61076-4-101 2 mm based connectors to increase connector pin counts and to facilitate the adoption of certain architectural features and capabilities. Physical features required to incorporate these connectors into the IEEE 1101.1 and IEC 60603-2 based architecture were detailed in the individual specifications. This document provides a means to specify this information without including extensive details in the systems specifications. The combination of Euroboard form factors and 2 mm connectors has been utilized in other system architectures and is anticipated to be included in future systems. This specification defines a variety of configurations that combine Euroboards and 2 mm connectors in a manner that facilitates references to such architecture in such current and future applications.
|ANSI/VITA 30.1-2002||2mm Connector Practice for Conduction Cooled Euroboards||This specification is intended to be a companion specification to other standards as referenced. Other uses for this specification are in no way prohibited. The aim is to ensure mechanical interchangeability of conduction-cooled circuit card assemblies in a format suitable for military and rugged applications and to ensure their compatibility with both conduction cooled chassis and commercial, air-cooled, single height (3U) and double-height (6U) x 160mm, Euroboard chassis.||ANSI Ratified|
|VITA 30.2-2001 (IEC)||Power Connector Equipment Practice||This document describes various separable connectors that can be used to conduct electrical current between two printed boards. Typical applications include power supplies or other power management devices. It has been developed to aid in the design of equipment where such connectors are typically found. The information included consists of interface and profile dimensions, printed board layout dimensions, suggested or actual signal and power pin assignments as well as information regarding standards that may exist for the connectors. No consideration is given to current carrying capacities of the connector systems nor to the optimization or validity of any pin assignment schemes, which may be included. Similarly, if connector locations are given relative to common industry board practices, they are not to be assumed to be the sole possible location of such connectors. Power connectors are defined, for the purpose of this standard, as separable connectors that are designed to provide current to devices at levels consistent with the overall operating power of the device. As such, they must have at least one (1) contact capable of carrying five (5) amps or more of electrical current.||Industry Technical Agreement|
|ANSI/VITA 31.1-2003 (R2009)||Gigabit Ethernet on VME64x Backplanes||This specification leverages the PICMG 2.16 packet Switched backplane specification that adds a switched network based on Gigabit Ethernet to CompactPCI backplanes. The PICMG 2.16 CompactPCI P3 connector has two Gigabit Ethernet ports for improved performance and redundancy. The CompactPCI P3 connector and the VME64x P0 connector are identical IEC 61076-4-101 2 mm based connectors and have the same placement on the backplane. This standard adopts the PICMG 2.16 P3 connector pin assignment for use on VME64x boards. This standard also adopts the definition of the fabric card described in PICMG 2.16. PICMG 2.16 compliant systems and VITA 31.1 systems can use the same switched fabric boards.||ANSI Ratified|
|ANSI/VITA 32-2003 (R2009)||Processor PMC||The complete physical (mechanical) and the environmental layers are retained as specified in the IEEE 1386 CMC ("Common Mezzanine Card") standard except as noted in this document. If the information in this document contradicts IEEE 1386 or IEEE 1386.1, this document takes precedence.
Processor PMC cards are used where modular attachment of a processor is desired. These processor PMC cards may be used in conjunction with PMC I/O cards, traditional PCI cards, or with directly attached PCI components. As such, Processor PMCs increase the modularity of a computer system and thus complement, rather than compete with, the existing family of PMC cards.
Processor PMC cards are expected to electrically operate with existing carrier boards (or motherboards); that is, while the carrier may be redesigned to take advantage of the enhanced functions that are offered by this standard, such a redesign should not be a requirement to insure proper operation. Indeed, Processor PMCs shall be specifically enabled to operate as master/host CPUs; otherwise, such cards revert to traditional PMC modes, operating as intelligent slave/target processor boards.when that support is required within PMC and Processor PMC designs.
|ANSI/VITA 35-2000 (R2011)||PMC-P4 Pin Out Mapping to VME P0 and VME64x P2||This specification provides pin mapping assignments between a PCI mezzanine Card (PMC) module's user IO connector (P4) and the VME host's user IO connector. Four mappings are provided.
Other standards such as Compact PCI (CPCI) which supports a PMC and a VME-P0 style connector on the host could also use this standard.
|ANSI/VITA 38-2003 (R2008)||Intelligent Platform Management Interface (IPMI) with VME||This specification is based on the PICMG 2.9 System Management specification and describes the additional requirements for implementing Intelligent Platform Management Interface (IPMI) in a VME system. IPMI describes a hardware independent interface between chassis sensors and the operating system. IPMI is particularly useful for managing servers and High Availability systems.||ANSI Ratified|
|ANSI/VITA 39-2003 (R2009)||PCI-X for PMC and Processor PMC||PCI-X is defined in the PCI-X Addendum to the PCI Local Bus Specification and is the basis for the updates in this document.The physical (mechanical) and the environmental layers are specified in the IEEE 1386 CMC ("Common Mezzanine Card") and IEEE 1386.1 PMC ("PCI Mezzanine Card"). VITA 32 Processor PMC standard incorporates a set of extensions to IEEE 1386/1386.1 creating a new class of CPU based PMC cards.||ANSI Ratified|
|ANSI/VITA 40-2003||Status Indicator Standard||The purpose of this specification is to provide the information needed to design service indicators for boards, subsystems, and enclosures.
This document describes a service indicator standard that seeks to be as compatible as possible with existing indicator standards and their extensions across different product markets. This standard addresses the meaning and application of specific colors to service indicators. This standard also defines and assigns meanings to specific approved behaviors or states for each color. It specifies where indicators must be placed and in what order, and it specifies luminance levels and viewing angles.
|ANSI/VITA 41.0-2006 (R2011)||VXS: VMEbus Switched Serial Base Specification||The VME Switched Serial (VXS) specification comprises this base standard defining physical features of VXS components, coupled with a set of protocol layer standards to define the specific serial interconnect used in a system implementation.
The VXS base specification defines physical features that enable high-speed communication in a VME compatible system. These features include: addition of a high speed connector to the VME64x board in the P0/J0 position, a 6U by 160mm by 6HP Eurocard format board with many high speed connectors which may act as a switch, and the backplane/chassis infrastructure needed to support these features. In addition to defining a high -speed connector in the P0/J0 area, VXS also defines alignment and keying features which may be used to protect this and future alternate connectors.
The ratio of one high-speed connector per payload board to many on the switch card lends itself to a star topology where each payload card is connected to a central switch. For higher reliability and/or load balancing, two switch cards may be used in a dual star configuration. Interswitch links may be included for reliability and load balancing reasons as well. Although this topology is not required it is a natural fit for the system features.
|ANSI/VITA 41.1-2006 (R2011)||VXS: InfiniBand Protocol Layer||The objectives of this document are:
- To assign 4X InfiniBand signals for communication over the data links defined in VITA 41.0 (the base VXS specification).
- To provide requirements, constraints and recommendations for the use of the InfiniBand data links.
- To provide requirements, constraints and recommendations for the use of InfiniBand in-band management.
- To provide requirements, constraints and recommendations for the use of I2C out-of- band management.
The requirements and design rules defined in this specification are intended to be consistent with the applicable sections of the InfiniBand Specification. It is expected that VXS.1 products will comply with InfiniBand Signal, Link, Transport, and Management layers in order to maximize interoperability with other InfiniBand hardware and software products.
|ANSI/VITA 41.2-2006 (R2011)||VXS: Serial RapidIO Protocol Layer||The objectives of this document are:
- To assign 4X Serial RapidIO signals for communication over the data links defined in VXS.0.
- To provide guidelines for the use of the Serial RapidIO data links.
- To provide guidelines for the use of Serial RapidIO in-band management. Out-of-band management.
- To provide guidelines for the use of I2C
The guidelines and design rules defined in this specification are intended to be consistent with the applicable sections of the Serial RapidIO Specification. It is expected that VXS.2 products will comply with Serial RapidIO Signal, Link, Transport, and Management layers in order to maximize interoperability with other Serial RapidIO hardware and software products.
|VITA 41.3||VXS: GbE Protocol Layer||The objectives of this document are:
- To assign 1000Mb/s baseband IEEE 802.3 signals for communication over the data links defined in VXS.0.
- To provide guidelines for the use of the 1000Mb/s baseband IEEE 802.3 links.
- To provide guidelines for the use of 1000Mb/s baseband IEEE 802.3 in-band management.
- To provide guidelines for the use of I2C out-of-band management.
The guidelines and design rules defined in this specification are intended to be consistent with the requirements of IEEE Std 802.3-2002. It is expected that VXS.3 products will comply with all the applicable clauses of IEEE Std 802.3-2002 to enable the use of standard hardware and software and maximize the potential for interconnection with other 1000Mb/s baseband IEEE 802.3 systems.
|Working Group - Draft|
|VITA 41.4||VXS: PCI Express Protocol Layer||The objectives of this document are:
- To assign 4X PCI Express signals for communication over the data links defined in VXS.0 (the base VXS specification).
- To provide requirements, constraints and recommendations for the use of the PCI Express data links.
- To provide requirements, constraints and recommendations for the use of PCI Express in-band management.
- To provide requirements, constraints and recommendations for the use of I2C out-of-band management.
The requirements and design rules defined in this specification are intended to be consistent with the applicable sections of the PCI Express Specification. It is expected that VXS.4 products will comply with PCI Express Signal, Link, Transport, and Management layers in order to maximize interoperability with other PCI Express hardware and software products.
|Working Group - Draft|
|ANSI/VITA 41.6-2009||VXS: 1x Gigabit Ethernet Control Channel Layer||The objectives of this document are:
- To define and assign 1X GigE signals for communication over signal sets currently defined as reserved for future use in VXS.0.
- To provide guidelines for the use of the GigE data links.
- To provide guidelines for the use of GigE System management.
- To provide guidelines for the use of GigE switching services and management.
The guidelines and design rules defined in this specification are intended to be consistent with the applicable sections of the IEEE 802.3 Specification.
|VITA 41.8||VXS: 10GbE Protocol Layer||Working Group - Draft|
|ANSI/VITA 42.0-2008||XMC: Switched Mezzanine Card Base Specification||Specific goals include supporting:
- A high-speed switched interconnect.
- Open, standardized technologies for switched fabrics.
- Standard PMC form factors.
- Compatibility with existing PMC specifications.
- PMC, XMC, or dual-mode mezzanine cards.
- PMC, XMC, or dual-mode carriers.
- Standard VME, CompactPCI, Advanced TCA, and PCI Express carriers.
- Standard PMC stacking heights.
- Optional conduction cooling.
In support of these goals, this document specifies the mechanical and generic electrical requirements necessary to serve as a basis for any number of protocol layer standards built on and complying with this standard.
|ANSI/VITA 42.1-2006||XMC: Parallel RapidIO Protocol Layer||This specification defines an open standard for supporting Parallel RapidIO switched interconnect protocol on the XMC form factor. The objectives of this document are:
- To assign Parallel RapidIO signals for communication over the high-speed connectors and data links defined in XMC.0.
- To provide guidelines for the use of the Parallel RapidIO data signals.
The guidelines and design rules defined in this standard are intended to be consistent with the applicable sections of the Parallel RapidIO Specification. It is expected that XMC.1 products will comply with Parallel RapidIO Physical, Transport, and Logical layers in order to maximize interoperability with other Parallel RapidIO hardware and software products.
|ANSI/VITA 42.2-2006||XMC: Serial RapidIO Protocol Layer||This specification defines an open standard for supporting the Serial RapidIO switched interconnect protocol on the XMC form factor. In light of this objective, specific goals include supporting:
- To assign 4X Serial RapidIO signals for communication over the switch connectors defined in XMC.0.
- To provide guidelines for the use of Serial RapidIO signals.
The guidelines and design rules defined in this standard are intended to be consistent with the applicable sections of the Serial RapidIO specification. It is expected that XMC.2 products will comply with Serial RapidIO Physical, Transport, and Logical layers to realize maximum interoperability with other Serial RapidIO hardware and software.
|ANSI/VITA 42.3-2006||XMC: PCI Express Protocol Layer||This specification defines an open standard for supporting PCI Express switched interconnect protocol on the XMC form factor. The objectives of this document are:
- To assign 1, 2, 4, 8, 16 and 32 Lane PCI Express interfaces, or Links for communication over the switch connectors defined in XMC.0.
- To provide guidelines for the use of PCI Express signals.
|ANSI/VITA 42.6-2009||XMC: 10 GbE Protocol Layer||This specification defines a standard for supporting 10 Gigabit Ethernet using XAUI switched interconnect protocol on the XMC form factor by the assignment of XAUI signals and by the provision of guidelines for the use of XAUI signals.
Products should comply with XAUI Physical, Transport, and Logical layers to ensure interoperability.
|VITA 42.10||XMC: General Purpose I/O||The objective of this specification is to supplement the XMC base specification requirements defined within VITA 42.0, in order to provide consistent pin assignments for commonly used interfaces on the secondary XMC connectors (P16 and P26). These interface definitions are limited to signal assignments on the XMC connectors, and do not change the electrical or data format functional definitions associated with any of the protocols addressed by this specification. This specification provides no definitions for interface link wiring on the carrier board or through the host system.
Interfaces defined in this specification include the following:
- Ethernet: 10/100/1000 BaseTX MDI ports
- USB: 1.1 and 2.0 ports
- RS-232 / RS-485 serial ports
- Serial ATA / Fibre Channel / SAS ports
Other interface ports, such as I2C serial links or video ports, may also be carried on the XMC secondary connectors. The system designer is responsible for managing signal assignments for those ports, as those assignments are outside the scope of this specification.
|Working Group - Draft|
|VPX: Base Specification||Commonly known as VPX, this specification family defines entirely new high-speed connectors in part to carry mappings for popular switched serial fabrics including Gigabit Ethernet, PCI Express, Serial RapidIO, InfiniBand, and Aurora. It also defines a new increased power envelope including a 48V profile, and additional cooling methods.
The base standard does not address the possible serial fabric configurations available in systems which utilize the standard.
|ANSI/VITA 46.1-2007||VPX: VMEbus Signal Mapping||This specification supplements the VITA 46 base specification with the definition for the VMEbus signals as mapped to a VITA 46 connector.||ANSI Ratified|
|ANSI/VITA 46.3-2012||VPX: 4x Serial RapidIO Signal Mapping||This specification supplements the VITA 46 base specification with the definition for the 4x Serial RapidIO signals as mapped to a VITA 46 connector.||ANSI Ratified|
|ANSI/VITA 46.4-2012||VPX: PCI Express Signal Mapping||This specification supplements the VITA 46 base specification with the definition for the PCI Express signals as mapped to a VITA 46 connector.||ANSI Ratified|
|ANSI/VITA 46.6-2013||VPX: Gbit Ethernet Control Plane Signal Mapping||This specification supplements the VITA 46 base specification with the definition for the Gbit Ethernet signals as mapped to a VITA 46 connector.||ANSI Ratified|
|ANSI/VITA 46.7-2012||VPX: 10Gbit Ethernet Signal Mapping||This specification supplements the VITA 46 base specification with the definition for the 10 Gbit Ethernet signals as mapped to a VITA 46 connector.||ANSI Ratified|
|VITA 46.8-VDSTU||VPX: InfiniBand||This specification supplements the VITA 46 base specification with the definition for the InfiniBand signals as mapped to a VITA 46 connector.||VITA Draft Standard for Trial Use|
|ANSI/VITA 46.9-2010||VPX: PMC/XMC Rear I/O Fabric Signal Mapping on 3U and 6U VPX Modules||Because of the numerous possibilities presented by combinations of 3U and 6U VITA46 carriers supporting single or dual width PMC and/or XMC mezzanines it is impractical to provide a fully comprehensive specification. Therefore, this standard will cover only the following combinations, which have been determined the most likely to be actually implemented in practice:
- 3U/6U VITA 46 carrier with PMC JN4 I/O mapping to backplane P2
- 3U/6U VITA 46 carrier with XMC JN6 I/O mapping to backplane P2
- 6U VITA 46 carrier with PMC JN4 I/O mapping to backplane P3 and P6
The overall objective of this specification is to detail the connection mapping between the defined mezzanine connector contact position and the associated backplane (BP) connector contact position for the above detailed combinations.
|ANSI/VITA 46.10-2010||VPX: Rear Transition Module||The objectives of this standard are:
- Define 6U by 80mm and 3U by 80mm Eurocard format rear transition modules suitable for air-cooled, ruggedized use;
- Define a suitable high-speed connector family for use in these plug-in modules;
- Make provision for power connections and I/O connections for the rear transition module.
|VITA 46.11-VDSTU||VPX: System Management||
This draft standard defines a system management architecture for VPX systems.
The objectives of this specification are:
|VITA Draft Standard for Trial Use|
|ANSI/VITA 47-2005 (R2007)||Environments, Design and Construction, Safety, and Quality for Plug-In Units||COTS plug-in units are widely used in commercial and military, ground and aerospace, mobile applications. Certification of COTS plug-in units, by supplying vendors, to this standard will facilitate the cost effective integration of these items in larger systems.||ANSI Ratified|
|ANSI/VITA 48.0-2010||VPX REDI: Ruggedized Enhanced Design Implementation Mechanical Base Specification||This document provides an overview of the associated plug-in units for air-cooling, conduction cooling, and liquid flow thru and spray cooling applications. Specific connector-mounting details are defined in VITA 46. The VITA 48 family of standards will define applicable detailed dimensions of key module and sub-rack interfaces. The implementations described in this standard are targeted for 3U and 6U form factor boards on 0.85 and 1.00 centers. However, the packaging approach presented is applicable to boards with other form factors, different connector series and can accommodate alternate module pitches.
The purpose of this specification is to define an overall approach to packaging modules to improve both their thermal and structural characteristics as well as incorporate the provisions for 2 level maintenance. In addition this standard will define the applicable environmental requirements of plug-in units to ensure successful integration into higher levels of assembly.
|ANSI/VITA 48.1-2010||VPX REDI: Mechanical Specifications for Microcomputers Using Air Cooling Applied to VPX||This specification defines the dimensions of associated plug-in units for air-cooling applications and connector-mounting details together with applicable detail dimensions of key sub-rack interfaces. The module assemblies defined by this standard will be compatible with two level maintenance applications.||ANSI Ratified|
|ANSI/VITA 48.2-2010||VPX REDI: Mechanical Specifications for Microcomputers Using Conduction Cooling Applied to VPX||This specification defines the dimensions of associated plug-in units for conduction cooling applications and connector-mounting details together with applicable detail dimensions of key sub-rack interfaces. The module assemblies defined by this standard will be compatible with two level maintenance applications.||ANSI Ratified|
|VITA 48.3||VPX REDI: Mechanical Specifications Using Liquid Cooling Applied to VPX, Manifold Below the Backplane||This specification defines the dimensions of associated plug-in units for liquid cooling applications and connector-mounting details together with applicable detail dimensions of key sub-rack interfaces. The module assemblies defined by this standard will be compatible with two level maintenance applications.||Working Group - Draft|
|ANSI/VITA 48.5-2010||VPX REDI: Mechanical Specifications Using Air Flow-through Cooling Applied to VPX||This specification establishes the design requirements for an air-flow-through cooled plug-in unit with a 6U form factor.||ANSI Ratified|
|ANSI/VITA 49.0-2009||VITA Radio Transport (VRT)||This specification defines a transport-layer protocol designed to promote interoperability between RF (radio frequency) receivers and signal processing equipment in a wide range of applications.||ANSI Ratified|
|ANSI/VITA 49.1-2009||VITA Radio Link Layer (VRL)||This specification specifies an optional encapsulation protocol for VITA-49.0 (VRT) packets.||ANSI Ratified|
|ANSI/VITA 51.0-2008 (R2012)||Reliability Prediction||This document provides an electronics failure rate prediction standard, and establishes a Community of Practice. It addresses the limitations of existing prediction practices with a series of subsidiary specifications that contain the "best practices" within industry for performing electronics failure rate predictions. The development of ANSI/VITA 51.0 and the subsidiary specifications is an effort to give the mean time between failure (MTBF) calculations consistency and repeatability.||ANSI Ratified|
|Reliability Prediction: MIL-HDBK-217 Subsidiary Specification||This specification provides standard defaults and methods to adjust the models in MIL-HDBK-217F Notice 2. This is not a revision of MIL-HDBK-217F Notice 2 but a standardization of the inputs to the MIL-HDBK-217F Notice 2 calculations to give more consistent results.||ANSI Ratified|
|ANSI/VITA 51.2-2011||Physics of Failure Reliability Predictions||It includes a discussion of the philosophy, context for use, definitions, models for key failure mechanisms, definition of the input data required, default values if technically feasible or the typical range of values as a guideline. It defines how modeling results are interpreted and used. It requires the documentation of modeling inputs, assumptions made during the analysis, modifications to the models and rationale for the analysis.||Working Group - Ballot|
|ANSI/VITA 51.3-2010||Qualification and Environmental Stress Screening in Support of Reliability Predictions||This specification provides rules, permissions, and observations to assure that cost effective Qualification and Environmental Stress Screening support valid reliability predictions and enhance electronics reliability. It includes a discussion of the systems engineering relationships between Qualification, Environmental Stress Screening, and reliability.||ANSI Ratified|
|ANSI/VITA 53.0-2010||Standard for Commercial Technology Market Surveillance||Technology refresh events are fueling the large majority of new DoD acquisition efforts in the post-"Perry memo" era of increased DoD reliance on commercial technology vendor design, production, support, and repair services. Preferred DMSMS management method for DoD programs.||ANSI Ratified|
|ANSI/VITA 57.1-2008||FMC: FPGA Mezzanine Cards Base Specification||This specification describes an IO mezzanine module, which shall connect to, but is not limited to, 3U and 6U form factor cards. This mezzanine module is in a smaller form factor, when compared to PMC/XMC modules and assumes that it will be connected to a FPGA device or other device with reconfigurable IO capability. This standard describes FMC IO modules and introduces an electro-mechanical standard that creates a low overhead bridge. This is between the front panel IO, on the mezzanine module, and an FPGA processing device on the carrier card, which accepts the mezzanine module.||ANSI Ratified|
|VITA 57.2||FMC: Metadata Description||XML metadata descriptions for FMC.||Working Group - Draft|
|ANSI/VITA 58.0-2009||Line Replaceable Integrated Electronics Chassis||The complete standard for a typical Line Replaceable Unit (LRU) would consist of the requirements contained herein along with the specific requirements contained in the dot specification for a particular type of LRU, e.g., an LRU designed to use liquid cooled, VITA 48 module as detailed in VITA 48.3.||ANSI Ratified|
|VITA 59.0||Rugged COM Express™||This specification VITA 59.0, Rugged System-On-Module Express RSE, describes an innovative step forward for the provision of high-speed serial interconnects for computer modules and makes such modules usable in harsh-environment applications.||Working Group - Draft|
|ANSI/VITA 60.0-2012||VPX: Alternative Connector for VPX||This specification describes VITA 60.0 Alternate Connector for VPX for VMEbus systems VITA 60.0 provides an alternative connector to the one specified in VITA 46.0, VPX Baseline Standard. Because the 46.0 and the 60.0 connectors are not intermateable a VITA 60.0 module will not plug into a VITA 46.0 backplane and vice versa. However, the VITA 60.0 draft standard provides VPX users with the flexibility to choose a VPX module and backplane connector combination for their specific application requirements.||ANSI Ratified|
|ANSI/VITA 61.0-2011||XMC 2.0||This standard, based upon VITA 42.0 XMC, defines an open standard for supporting high-speed, switched interconnect protocols on an existing, widely deployed form factor, but utilizing an alternate, ruggedized, high speed mezzanine interconnector known as VITA 61 XMC 2.0.||ANSI Ratified|
|ANSI/VITA 62.0-2012||VPX: Power Supply||Defines the power generation requirements for a module that can be used to power systems that support a VITA 62 slot on the VPX backplane. VITA 62 uses the standard VPX 3U/6U form factor and complies to the requirements defined in VITA 48.0. VITA 62 has utility functionality that includes N+1 failover, VBAT and 50ms holdup. VITA 62 defines a set of connectors that mate with a VITA 62 compatible backplane such that VITA 62 module can be plugged into the backplane.||ANSI Ratified|
|VITA 63||VPX: KVPX||Alternate connector for VPX||Working Group - Draft|
|OpenVPX Architectural Framework for VPX||
The OpenVPX System Specification was created to bring versatile system architectural solutions to the VPX market. Based on the extremely flexible VPX family of standards, the OpenVPX standard uses module mechanical, connectors, thermal, communications protocols, utility, and power definitions provided by specific VPX standards and then describes a series of standard profiles that define slots, backplanes, modules, and standard development chassis.
|ANSI/VITA 66.0-2011||VPX: Fiber Optic Interconnect||This specification defines a family of blind mate Fiber Optic interconnects for use with VITA 46 backplanes and plug-in modules.||ANSI Ratified|
|ANSI/VITA 66.1-2011||VPX: Optical Interconnect On VPX - MT Variant||MT Mechanical Mating I/F Definition
MT Optical Mating I/F Definition
|ANSI/VITA 66.2-2013||VPX: Optical Interconnect On VPX - ARINC 801||ARINC 801 Mechanical Mating I/F Definition
ARINC 801 Optical Mating I/F Definition
|ANSI/VITA 66.3-2012||VPX: Optical Interconnect On VPX - Expanded-Beam||Expanded Beam Mechanical Mating I/F Definition
Expanded Beam Optical Mating I/F Definition
|VITA 66.4||VPX: Optical Interconnect On VPX - MT Variant||Half Size Optical Interconnect||Working Group - Draft|
|ANSI/VITA 67.0-2012||VPX: Coaxial Interconnect||This specification establishes a structure for implementing blind mate analog coaxial interconnects with VPX backplanes and plug-in modules, and to define a specific family of interconnects and configurations within that structure.||ANSI Ratified|
|ANSI/VITA 67.1-2012||VPX: Coaxial Interconnect , 3U, 4 Position SMPM Configuration||This specification details the configuration and interconnect within the structure of VITA 67.0 enabling a 3U VITA 46 interface containing multiposition blind mate analog connectors with up to 4 SMPM contacts.||ANSI Ratified|
|ANSI/VITA 67.2-2012||VPX: Coaxial Interconnect , 6U, 8 Position SMPM Configuration||This specification details the configuration and interconnect within the structure of VITA 67.0 enabling a 6U VITA 46 interface containing multiposition blind mate analog connectors with up to 8 SMPM contacts.||ANSI Ratified|
|VITA 67.3||VPX: Coaxial Interconnect , 6U, 4 Position SMPM Configuration||This specification details the configuration and interconnect within the structure of VITA 67.0 enabling a 6U VITA 46 interface containing multiposition blind mate analog connectors with up to 4 SMPM contacts.||Working Group - Draft|
|VITA 68.0||VPX: Compliance Channel||This specification defines a VPX compliance channel including common backplane performance criteria required to support multiple fabric types across a range of defined baud rates.||Working Group - Draft|
|VITA 69.0||Common Glossary||Glossary of technical terms commonly used in VITA standards.||Working Group - Draft|
|VITA 70.0||Common Standard Template||Standard formats to be used for VITA standards. VITA Member use only.||Working Group - Draft|
|VITA 73.0-2012 VDSTU||Small Form Factor||Provides a standard mechanical format for standardization of switched serial interconnects for small form-factor applications, with specific concern taken to allow deployment in ruggedized environments.||VITA Draft Standard for Trial Use|
|VITA 74.0-2012 VDSTU||Nano Small Form Factor||Provides a standard mechanical format for standardization of switched serial interconnects for small form-factor applications, with specific concern taken to allow deployment in ruggedized environments.||VITA Draft Standard for Trial Use|
|VITA 75.0-2012 VDSTU||Rugged Small Form Factor - Base Standard||This draft standard for a rugged small form factor describes overall subsystem attributes such as the envelope of the subsystem (box) and the organization of the dot specifications.||VITA Draft Standard for Trial Use|
|VITA 75.11-2012 VDSTU||Rugged Small Form Factor - Subsystem I/O Interfaces||This draft standard for a rugged small form factor describes the standardization of front panels, connectors, I/O signal pin assignments, and power for VITA 75 subsystems.||VITA Draft Standard for Trial Use|
|VITA 75.20-2012 VDSTU||Rugged Small Form Factor - Cooled via Free Air Convection||This draft standard for a rugged small form factor describes the standardization of mounting and cooling for free air convection cooled VITA 75 subsystems.||VITA Draft Standard for Trial Use|
|VITA 75.22-2012 VDSTU||Rugged Small Form Factor - Cooled via Conduction to Cold Plate||This draft standard for a rugged small form factor describes the standardization of mounting and cooling for conduction to a cold plate cooled VITA 75 subsystem.||VITA Draft Standard for Trial Use|
|VITA 76||High Performance Cable Standard||Define a standard cable for box to box interconnection.||Working Group - Draft|
|VITA 78||SpaceVPX Systems||
This document describes an open standard for creating high performance fault tolerant interoperable backplanes and modules to assemble electronic systems for spacecraft and other high availability applications. Such systems will support a wide variety of use cases across the aerospace community. This standard leverages the OpenVPX standards family and the commercial infrastructure that supports these standards in non-space applications.
VITA is currently soliciting members to join the working group. Contact VITA if you are interested in participating in this effort.
|Working Group - Draft|
|VITA 79||Embedded Photonics||
Develop a standard based on work done by the JEDEC 13.6 subcommittee.
VITA is currently soliciting members to join the working group. Contact VITA if you are interested in participating in this effort.
|Working Group - Draft|
|VITA 80||Interoperability||Develop a method for testing interoperability among VPX modules.||Working Group - Draft|