VME Technology Specifications
VME technology continues to be a favorable choice as an industrial embedded computing architecture. Many current users have taken advantage of the long life cycle of VME products and have refreshed their product lines with the vast selection of VME products on the market. New projects are leveraging the advancements in VME technology with an eye on performance and the life cycle advantages of VME.
The VME Technology family of specifications has grown significantly since its inception. VMEbus has expanded from the original family of a core VME32 parallel bus specification, a VME Subsystem bus, and a VME serial interconnect to today's broad family of complementary state-of-the art specifications.
As the serial switch fabric solutions that include Gigabit Ethernet, PCI Express, RapidIO, StarFabric, Infiniband and other alternatives gain popularity and additional usage to form critical mass in the industry, specific purpose parallel and serial subsystem buses will start sharing market space by solving different problems within tomorrow's embedded systems. VME will evolve to incorporate the appropriate alternatives.
VME technology includes several mezzanine specifications that have been optimized for use in VME environments. Low profile, small form factor mezzanine solutions of various types have been developed with several obtaining ANSI approval. IP modules, M-modules, PC.MIP, and the very popular PMC modules all work effectively in VME applications. These continue to evolve as technology and application needs change.
Several system management and support specifications have also been ratified that make the development of VME systems easier with more robust system management. Proposals continue to be submitted and considered for addition to the VME Technology family to improve VME's utilization in complex systems.
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The VME Standards Organization (VSO) and ANSI have ratified nearly thirty supporting standards over the past 10 years, with several more in working group status at this time. These standards support the continued evolution of the core VMEbus technology to ensure a solid foundation for the future.
| Specification Reference Number | Common Name / Short Description | Detail Description | Status |
| ANSI/VITA 1.0-1994 (R2002) | VME64 Standard - This standard covers the main body of the VMEbus specification. It includes both 32 bit and 64 bit usage. Reaffirmed in 2002. | The VME64 specification establishes a framework for 8-, 16-, 32, and 64-bit parallel-bus computer architectures that can implement single and multiprocessor systems. This bus includes the initial four basic subbuses: (1) data transfer bus, (2) priority interrupt bus, (3) arbitration bus, and (4) utility bus. The data transfer bus will support 8-, 16-, 32-, and 64-bit data transfers in multiplexed and non multiplexed form. The transfer protocols are asynchronous with varying degrees of handshaking dependent on the speeds required. The priority interrupt subsystem provides real-time interrupt services to the system. The allocation of bus mastership is performed by the arbitration subsystem which allows the implementation of several prioritization algorithms. The utility bus provides the system with power plus power-up and power-down synchronization. The mechanical specifications of boards, backplanes, subracks, and enclosures are based on IEC 297 and IEEE 1101.1 specifications, also known as the Eurocard form factor. Additional standards exist that can be used as sub-busses to this architecture for data transfer transactions, peripheral interfaces and intra-crate communications among compatible modules. | Released |
| ANSI/VITA 1.1-1997 (R2003) | VME64x Extensions - This standard covers extensions to the VME64 specification including the 160 pin connector, geographical addressing, and added power pins. Reaffirmed in 2003. | This standard is an extension of the ANSI/VITA 1-1994, VME64 Standard. It defines a set of features that can be added to VME32 and VME64 boards, backplanes and subracks. These features include a 160 pin connector, a P0 connector, geographical addressing, voltages pins for 3.3V, a test and maintenance bus, and EMI, ESD, and front panel keying per IEEE 1101.10. | Released |
| ANSI/VITA 1.3-1997 (R2003) | VME64x 9U x 400 mm Format - This standard defines a 9U x 400 mm board layout for use within the VMEbus framework. Reaffirmed in 2003. | This standard is an extension of the ANSI/VITA 1-1994, VME64 Standard. It defines 9U x 400 mm boards, backplanes and subracks and is referred to as VME64x-9U. The VME64x Standard expanded the features of VME64 mainly by using a new 160 pin connector. These and other features in the VME64x Standard gained the interest of the Telecommunications Industry and the Physics Research Community. A major concern in both groups was a larger board format yet keeping as much compatibility with the existing VME standards as possible. This standard is a response to these needs. |
Released |
| ANSI/VITA 1.5-2003 | VME 2eSST - This standard defines a new VME protocol that allows data transfers of up to 320 Mbytes/second. | This standard is an extension of the ANSI/VITA 1-1994, VME64 and ANSI/VITA1.1-1997, VME64x standards. It defines a new transfer protocol, based upon source synchronous concepts, that permits the VMEbus to operate at rates up to 320MB/s. As technology improves, this rate can be extended to higher levels. The 2eSST protocol requires low skew between signals and monotonic rising and falling edges on the signals. To meet these requirements, limited length backplanes, special backplane topologies and/or enhanced transceivers are required. The enhanced bus transceivers should have controlled rise and fall times, tightly defined thresholds, low part to part skew and LVTTL levels. During the development of this standard, specific transceivers were developed to meet these requirements. Products designed to this specification remain backward compatible with previous generations of VMEbus products. |
Released |
| ANSI/VITA 1.6-2000 | Keying for Conduction Cooled VME64x | This standard is an extension of the ANSI/VITA 1.1-1997, VME64x Standard. It defines an alternate keying system that can be added to VME64x boards and backplanes in a conduction cooled environment (IEEE 1101.2) where keying as defined in the VME64 Extensions standard cannot be applied. | Released |
| ANSI/VITA 1.7-2003 | Increased Current DIN Connector - This standard describes increased current levels, test methods, test data and compliance criteria for 3 row DIN and 5 row DIN connectors when used in VME, VME64 and VME64 Extension P1/J1 and P2/J2 pin out arrangements. | This standard describes increased current levels, test methods, test data and compliance criteria for 3 row DIN and 5 row DIN connectors when used in VME, VME64 and VME64 Extension P1/J1 and P2/J2 pin out arrangements. The P1/J1 and P2/J2 current rating limits of the 3 row DIN and 5 row DIN connector pins listed in the DIN41612, IEC 603-2 and 61076-4-113 specifications are based on full loading of the connector. In VME, VME64, and VME64 Extensions applications, the power pins represent only a small fraction of the total number of pins and are spread throughout the connector. The remaining pins are used to carry electrical signals, which add a negligible heating contribution. The net effect is that the connector heating is less, which allows a higher current carrying capacity. Power contacts of connectors tested and certified in accordance with this standard are capable of passing 2.0 amps per contact on a selected group of pins. The standard has been verified by testing connectors from multiple vendors and it has been developed and approved by a broad cross-section of the VMEbus community. |
Released |
| ANSI/VITA 3-1995 (R2002) | Board Level Live Insertion - This standard defines several methodologies for using VMEbus modules in a live insertion framework. Reaffirmed in 2002. | Advances in technology allow increased functionality on same sized boards. Thus, VMEbus boards and system designs are greatly increasing in capability with increased demand for highly reliable and easily maintainable systems. This document identifies methodologies through which a faulty board can be removed from a system and a replacement board can be inserted while the system continues to operate. The primary motivation for supporting Board Level Live Insertion within the VMEbus environment is to enhance the current VMEbus standard while maximizing the use of existing off-the-shelf VMEbus products. | Released |
| ANSI/VITA 4.0-1995 (R2002) | IP Module - This standard defines the requirements for a business card sized mezzanine module printed circuit board. Reaffirmed in 2002. | This standard defines a versatile module, known as an "IP module." These modules provide a convenient method of implementing a wide range of I/O, control, interface, slave processor, analog and digital functions. IP modules, about the size of a traditional business card, mount parallel with a host Carrier board, which provides host processor or primary bus interfacing, as well as mechanical means for connecting the IP module's I/O to the outside world. Typical Carriers include standalone processors, DSP based carriers, as well as desktop buses and VME based boards. This specification includes mechanical, host bus electrical, and logical definition of I/O space, memory space, identification space, interrupts, DMA, and reset functions. Two physical sizes, two fixed clock rates, and multiple data width sizes to 32-bits are defined. VITA maintains a registry of identification numbers for IP Modules. |
Released |
| ANSI/VITA 4.1-1996 (R2003) | IP I/O Mapping to VME64x - This standard defines the pin assignments from IP Modules to the VME64x P0 and P2 connectors. Reaffirmed in 2003. | With the development of the VME64x, 205 user defined I/O pin are available for rear backplane I/O. It is practical to route multiple IP's I/O through the VME64x backplanes. This standard defines the mapping of the 50 user defined I/O pins from the IP module (ANSI/VITA 4-1995 (R2002)) I/O connectors to VME64x board's rear I/O connectors in a consistent method across all VME64x boards, backplanes and rear I/O transition boards. | Released |
| ANSI/VITA 5.1-1999 (R2004) | RACEway Interlink - This standard defines a high speed circuit switched point to point interconnect for use between VMEbus modules via the P2 connector | This standard provides a specification of the data link protocol and physical interface of a high performance extension to the VMEbus standard. This extension consists of high bandwidth, low latency interconnects across a VMEbus computer chassis backplane using the P2 connector. Bi-directional connectivity between boards in a VMEbus chassis is achieved through the use of a network of crossbar switches with point-to-point interconnects. RACEway Interlink is a VMEbus enhancement that can deliver up to 3.2 Gbytes/sec of scalable bandwidth over rows A, C, D and Z of the P2 connector in a standard VMEbus chassis. In addition to increased bandwidth, RACEway Interlink offers: 1) low latency, deterministic transactions, 2) concurrent point-to-point transactions for multiple simultaneous transfers, and 3) scalable bandwidth so total bandwidth increases as more slots are added. Many new applications, especially those with multiple processors and multiple real-time I/O interconnects, require these capabilities. In addition to being backward-compatible with VMEbus backplanes, RACEway Interlink has the following characteristics:
|
Released |
| VITA 5.2 | RACEway++ | Enhancements to ANSI/VITA 5.1 to support RACEway ++ features. | Working Group |
| ANSI/VITA 6.0-1994 (R2002) | SCSA - This standard defines an isochronous backplane bus for telephony applications on the VMEbus P2 connector. Reaffirmed in 2002. | The Signal Computing System Architecture (SCSA) specification establishes a framework for the inter- and intra-system transfer of serial media data and control information oriented toward the development of high density call and voice processing products and systems. The SCSA architecture is application specific and is embodied as a family of buses that are defined in this physical layer of the specification to reside on the VMEbus J2/P2 connector. The SCSA buses coexist with products compliant with ANSI/VITA 1-1994, VME64. SCSA at the physical level consists of two separate subbuses, a sixteen line, TDM data transfer bus called the SCbus, and a serial, peer-to-peer communication link called the SCmessage bus. The primary purpose of the SCbus is to support the exchange of real time telephonic voice, facsimile, data, video and other media streams. The purpose of the SCmessage bus is to transport interprocess control and status messages. This specification defines only the physical and data link OSI layers of the eventual four layer transport facility. The SC data transport bus is a synchronous, byte-serial, continuously framed bus organized as 16 serial data paths each divided into 32, 64, or 128 eight bit timeslots with a frame rate of 8,000 per second in order to accommodate intra-system telephonic voice and data transfers. The message bus is an HDLC framed, 2 Mbps, CSMA/CD packet bus that is bit-synchronized with the data transport bus. This specification covers the hardware specific elements of the VME-SCSA subbus including the message bus OSI protocol layers 1 and 2. Subsequent specifications provide an interface definition for the device specific software layer that provides compatibility between compliant VME-SCSA products and available upper layer SCSA resource management application programming interface(api) and other application software. |
Released |
| ANSI/VITA 6.1-1996 (R2003) | SCSA Extensions - This standard provides feature extensions to the ANSI/VITA 6 standard. | Addition of SCSA extensions to ANSI/VITA 6.0. | Released |
| ANSI/VITA 10-1995 (R2002) | SKYchannel - This standard defines a packet switched cross bar interconnect that runs on the VMEbus P2 connector. Reaffirmed in 2002. | This standard provides a specification of the data link protocol and physical interface of a high performance packet bus extension to the VME standard. This extension consists of high bandwidth, low latency packet bus transfers between VMEbus modules using the P2 connector and a network of crossbar designs. This standard describes a high performance SKYchannel Packet Bus architecture that is fully compatible with the VMEbus standards ([1], [2]). This standard addresses communication between VME boards using the P2 connector. This includes the physical layer for communication between the VME board and a SKYchannel Backplane through VME P2/J2, and the data link layer for communication from board to board. This standard does not address the physical layer for running SKYchannel within a SKYchannel Backplane or group of Backplanes, which is considered an implementation detail. The standard includes specifics of the packet protocol, signals, waveforms, timing diagrams and mechanical specifications. |
Released |
| ANSI/VITA 12-1997 (R2002) | M-Module - This standard defines a mezzanine module specification for small sized printed circuit boards. Reaffirmed in 2002. | This specification defines minimum mechanical and electrical characteristics of M-Modules, a method of implementing modular circuit boards with specific functions that can be used to add functionality to other larger printed circuit boards. For special requirements, a third row can be added to the base board connection. This is described in the mechanical specification. The use of the additional signals or extended use of existing signals (in compliance with the basic electrical specification) can be standardized to a certain extent. Therefore, certain signals and signal groups are defined in the extended electrical specification as regards their function, timing and electrical characteristics. Modules complying with these additional specifications are designated MA-Modules. |
Released |
| ANSI/VITA 13-1995 | VMEbus Pin Assignment Standard for ISO/IEC 14575 (IEEE Std. 1355-1995 (H.I.C.)) - This standard defines a pin assignment on VME for the Heterogeneous Interconnect protocol defined in IEEE 1355. | This specification defines a standard pin assignment for ISO/IEC 14575 (IEEE Std. 1355-1995 (H.I.C.) heterogeneous interconnect on the VMEbus. DS-SE links provide a bi-directional point to point communications link made up of a data and a strobe signal in each direction. Complete electrical and protocol definitions are given in the IEEE 1355 Standard for Heterogeneous InterConnect (HIC) (Low Cost Low Latency Scaleable Serial Interconnect for Parallel System Construction). The low level protocols employed on these links provide the packet structures and routing mechanisms required to allow higher level protocols such as ATM (ITU I.321), Fibre Channel (ANSI X3T11) or the Scaleable Coherent Interface - SCI (IEEE 1596-1992) to be supported across each link. This standard defines the mechanisms to be used for the implementation of DS-SE links within a VMEbus architecture. No mandatory topologies are defined, rather the standard creates a framework whereby the technology may be utilized in many diverse applications ranging from multiprocessor systems where there is a requirement for scaleable low latency links through to communication systems supporting ATM and other high level protocols. |
Released |
| ANSI/VITA 17.0-1998 (R2004) | Front Panel Data Port (FPDP) - This standard defines a point to point data interconnect for use on front panel Eurocard modules. | This standard provides a specification of the protocol and mechanical characteristics of the Front Panel Data Port. This extension to the VME standard consists of a multi-drop synchronous parallel non-addressable bus connection between multiple boards in a single chassis. The connection is made to a connector on the front panel of each board by means of an eighty conductor ribbon cable. The purpose of this specification is to allow products to be designed to work with other FPDP products. The degree of interoperability may depend on the layers of functionality above the physical and data link layers. These higher layers are not part of this specification. |
Released |
| ANSI/VITA 17.1-2003 | Serial Front Panel Data Port - This standard defines "Serial FPDP", a high-speed low-latency serial communications protocol for use in high-speed data transfer applications, typically using a fiber optic link. | This standard defines "Serial FPDP", a high-speed low-latency serial communications protocol for use in high-speed data transfer applications, typically using a fiber optic link. As the name implies, it is directly related to Standard Front Panel Data Port (FPDP), deriving its serial protocol from the defined protocol and control signals of FPDP. This Serial FPDP standard supports three link speeds: 1.0625 Gbaud, 2.125 Gbaud, and 2.5 Gbaud. These three link speeds can support data transfer rates in excess of 105 MBps, 210 MBps, and 247 MBps respectively. Included in this definition are the data frame structure, the link layer protocol, and the physical media requirements. The purpose of this standard is to allow products to be designed to work with other Serial FPDP products. The degree of interoperability will depend on the specific options implemented. Although all options are supported by this standard, not all products are required to support all options. |
Released |
| VITA 17.2 | Serial Front Panel Data Port Extensions - This standard defines a 10Gbit Serial FPDP. | The main objective of VITA 17.2 is to increase the bandwidth of the link. This can be done by both increasing the speed of the link, and by providing the ability to channel bonding several lanes together. The VITA 17.2 protocol is designed to provide functional compatibility with both VITA 17 and VITA 17.1 protocols, while providing increased bandwidth. In addition, the VITA 17.2 protocol is designed to provide a minimum footprint, and to maximize the use of dedicated hardware that is found in current FPGAs. |
Working Group |
| VITA 19.0 | BusNet Overview - This document is not a recognized ANSI standard and will not be submitted for standardization. It is provided here for completeness with the ANSI/VITA 19.1 and 19.2 standards. | Today all modern bus systems, especially the VMEbus system, offer facilities to share data between multiple processors connected to the same backplane (network); still, users must expend considerable programming effort to make use of these facilities. The VME BusNet Protocol is designed to provide a common and unique method for use by two or more devices (participants or peers) for network communication across a backplane. Because the VME BusNet Protocol is context independent, which means the contents of the packets sent across the backplane are independent of the protocol, most high-level networking protocols available today can be used by peers on the same VMEbus backplane without the need for a second physical interconnection between the participants. This document is not the BusNet specification. It is a summary document that gives an overview of the current BusNet specifications and their draft or approval status. The BusNet specification has been divided into several independent documents. This document (VITA 19.0- 1997) is not an approved document and will never be an approved document. It is being provided strictly for informational purposes. The goal of the BusNet project is to develop a VMEbus-based network which mimicked identically the functionality of a standard 10-Mbit Ethernet TCP/IP network. Because modern networks follow a layered model, the physical transport-layer (the Ethernet cable and adapter) can be replaced by the VMEbus; giving the overlying network-layers and applications the functionality of a standard Ethernet network while actually using the VMEbus as the transport medium. The primary advantage to this approach is that all software that uses standard network protocols (e.g., IP) can work without modification over the VMEbus backplane while eliminating the need for separate Ethernet hardware, cables, and connectors and taking advantage of the higher bandwidth of the VMEbus. It is important to distinguish IP compatibility from Ethernet compatibility. While the original BusNet goals were to insure that TCP/IP could be run over the VMEbus as though it was a 10- Mbit Ethernet cable, the design of the BusNet specification does not preclude the use of other standard networking protocols. That is, virtually any network protocol that can be used on a 10-Mbit Ethernet cable should also be compatible with BusNet. |
Cancelled |
| ANSI/VITA 19.1-1998 | BusNet Media Access Control - This standard defines the media access control layer for the BusNet backplane software protocol. | The VME BusNet Protocol is designed to provide a common and unique method for use by two or more devices (participants or peers) for network communication across a backplane. Because the VME BusNet Protocol is context independent, which means the contents of the packets sent across the backplane are independent of the BusNet protocol, most high-level networking protocols available today can be used by peers on the same VMEbus backplane without the need for a second physical interconnection between the participants. This specification defines packet control structures, packet buffer structures, configuration parameters, and procedures for locating BusNet participants and moving packets between BusNet participants. The intention is to move any network packet over the VMEbus without having knowledge of the actual network packet type. This specification does not define an API. It defines only data structures, configuration parameters, and state transitions for manipulating those data structures. |
Released |
| ANSI/VITA 19.2-1998 | BusNet Link Layer Control - This standard defines the link layer control layer for the Busnet backplane software protocol. | The VME BusNet Protocol is designed to provide a common and unique method for use by two or more devices (participants or peers) for network communication across a backplane. Because the VME BusNet Protocol is context independent, which means the contents of the packets sent across the backplane are independent of the BusNet protocol, most high-level networking protocols available today can be used by peers on the same VMEbus backplane without the need for a second physical interconnection between the participants. This specification defines additional elements in the packet buffer structures defined by VITA 19.1 to be used for multiplexing and demultiplexing network packets on behalf of multiple upper network stacks. This BusNet layer provides a function similar to the type field in an Ethernet packet or a PPP packet. This specification does not define an API. It defines data structures, configuration parameters, and procedures for manipulating those data structures. |
Released |
| ANSI/VITA 20-2001 (R2005) | Conduction Cooled PMC (CCPMC) - This standard defines the mechanical requirements for compliance with conduction cooled PMC modules. Revised in 2005. | This standard defines the methodology and implementation details to allow the creation of conduction cooled PMC modules to ensure electrical and physical compatibility with various host card modules onto which conduction cooled PMCs are mounted. The goal of this standard is to allow the intermixing of different vendors air and conduction cooled PMC modules onto air and/or conduction cooled host card modules to the maximum extent possible. Intermixing of air cooled PMC and conduction cooled PMC mezzanine modules on a single type of base/host card is generally intended for development purposes only. |
Released |
| ANSI/VITA 23-1998 (R2004) | VME64 Extensions for Physics - This standard defines a series of recommended practices for the use of VMEbus in the physics community. | This document is intended to be used internationally in physics applications and in other fields with similar requirements. It provides implementation rules, recommendations, and guidelines that enhance the use of the VMEbus standard as specified in ANSI/VITA 1-1994, VME and ANSI/VITA 1.1, VME64 Extensions. The VMEbus standards are the basis for this document. Hardware and software produced according to this document are in full compliance with the VMEbus standards. The Rules, Recommendations, Observations, etc. in this document are complementary to and compliant with existing VME standards. The Rules in this document are based on either Rules, Recommendations or Suggestions in a VME standard or draft standard as well as items not addressed by VME standards. This document is generally consistent with the NIM/VME-P document 9612, "VMEbus for Physics Applications", that has served as a working group approach, and has also utilized items from the CERN VSC "Recommended Practices" document. |
Released |
| ANSI/VITA 25-1997 | VISION (Versatile I/O Software Interface for Open-bus Networks) - This standard defines a software application interface for VMEbus modules | VISION (Versatile I/O Software Interface for Open-bus Networks) specifies a standard way to move data among entities connected by a bus, and possibly across a network. VISION is intended to be implemented on bus masters (which initiate data transfers with slaves). Also, another computer on the network may act as a VISION client and read or write data via a VISION master (acting as a server). Although originally intended only for VMEbus, VISION can, through the use of "components", be applied to other similar technologies. A VISION component is a software "plug-in" which encapsulates the support for a particular bus, set of protocols and access mechanisms. It is like a driver, although it may not be implemented as a driver on all platforms. With components, a VISION implementation may be used to integrate hybrid systems under a single software interface. | Released |
| ANSI/VITA 26-1998 (R2003) | Myrinet - This standard defines a packet switched interconnect protocol for implementation in a VMEbus environment. Reaffirmed in 2003. | This standard describes the high-performance, inter-computer, Myrinet packet network that is fully compatible with existing VMEbus standards and their extensions. This standard addresses communication between VME boards using interconnect either on the front panel or on the backplane. The communication may use cables or an overlay (such as a backplane). The standard defines the interface between a VME board and Myrinet, allowing not only intra-subrack, board-to-board communication, but also a uniform extension for inter-subrack, inter-cabinet, and even local-area-network (LAN) communication. This standard includes, either directly or by reference, the specification of the Data Link level, timing information, character set, signals, and the details of the connectors. | Released |
| ANSI/VITA 29-2001 | PC.MIP - This standard defines the mechanical form factor and the pin assignments for a small form factor mezzanine module based on the PCI bus. | This standard defines the mechanical and electrical specification for compliance with the PC-MIP mezzanine module. The mechanical specifications are defined in this standard. The electrical specifications are based on the PCI bus. This document provides the appropriate pin assignments. | Released |
| ANSI/VITA 30.0-2000 | 2mm Connector Practice for Euroboard Systems - This standards provides the dimensions for Euroboard systems that use 2mm connectors. | This standard defines an equipment practice based on a combination of 2 mm connectors, per IEC 61076-4-101, and subracks, racks and printed boards based on the Euroboard form factors. In the late 1980's, the VME specification expanded for 64 bit data and address capability, which also affected the specified connectors used at the plug-in module interface. The designers utilized IEC 61076-4-101 2 mm based connectors to increase connector pin counts and to facilitate the adoption of certain architectural features and capabilities. Physical features required to incorporate these connectors into the IEEE 1101.1 and IEC 60603-2 based architecture were detailed in the individual specifications. This document provides a means to specify this information without including extensive details in the systems specifications. The combination of Euroboard form factors and 2 mm connectors has been utilized in other system architectures and is anticipated to be included in future systems. This specification defines a variety of configurations that combine Euroboards and 2 mm connectors in a manner that facilitates references to such architecture in such current and future applications. |
Released |
| ANSI/VITA 30.1-2002 | 2mm Connector Practice for Conduction Cooled Euroboard Systems - This standard defines the dimensions for conduction cooled Euroboards when used with 2mm connectors. | This document describes mechanical characteristics for conduction-cooled versions of Euroboard-based circuit card assemblies utilizing 2mm connectors. This standard is intended to be a companion standard to other standards as referenced. Other uses for this standard are in no way prohibited. The aim is to ensure mechanical interchangeability of conduction-cooled circuit card assemblies in a format suitable for military and rugged applications and to ensure their compatibility with both conduction cooled chassis and commercial, air-cooled, single height (3U) and double-height (6U) x 160mm, Euroboard chassis. | Released |
| IEC/VITA 30.2-2001 | Separable Power Connectors - This standard defines the interface dimensions and printed board layouts of a variety of separable power connectors. | This standard describes various separable connectors that can be used to conduct electrical current between two printed boards. Typical applications include power supplies or other power management devices. It has been developed to aid in the design of equipment where such connectors are typically found. The information included consists of interface and profile dimensions, printed board layout dimensions, suggested or actual signal and power pin assignments as well as information regarding standards that may exist for the connectors. No consideration is given to current carrying capacities of the connector systems nor to the optimization or validity of any pin assignment schemes, which may be included. Similarly, if connector locations are given relative to common industry board practices, they are not to be assumed to be the sole possible location of such connectors. Power connectors are defined, for the purpose of this standard, as separable connectors that are designed to provide current to devices at levels consistent with the overall operating power of the device. As such, they must have at least one (1) contact capable of carrying five (5) amps or more of electrical current. | Industry Technical Agreement |
| ANSI/VITA 31.1-2003 | Gigabit Ethernet on VME64x Backplanes - This standard defines a pin assignment and interconnection methodology for implementing a 10/100/1000BASE-T Ethernet switched network on a ANSI/VITA 1.1 VME64x backplane. | This standard defines a pin assignment and interconnection methodology for implementing a 10/100/1000BASE-T Ethernet switched network on a VME64x backplane. This specification leverages the PICMG 2.16 packet Switched backplane specification that adds a switched network based on Gigabit Ethernet to CompactPCI backplanes. The PICMG 2.16 CompactPCI P3 connector has two Gigabit Ethernet ports for improved performance and redundancy. The CompactPCI P3 connector and the VME64x P0 connector are identical IEC 61076-4-101 2 mm based connectors and have the same placement on the backplane. This standard adopts the PICMG 2.16 P3 connector pin assignment for use on VME64x boards. This standard also adopts the definition of the fabric card described in PICMG 2.16. PICMG 2.16 compliant systems and VITA 31.1 systems can use the same switched fabric boards. |
Released |
| ANSI/VITA 32-2003 | Processor PMC - This standard incorporates a set of extensions to the IEEE 1386.1 PMC ("PCI Mezzanine Card") standard which creates a new class of CPU based PMC cards referred to in this standard as Processor PMC cards. The standard retains electrical signaling compatibility with existing PMC cards. | This standard incorporates a set of extensions to the IEEE 1386.1 PMC ("PCI Mezzanine Card") standard which creates a new class of CPU based PMC cards referred to in this standard as Processor PMC cards. The standard retains electrical signaling compatibility with existing PMC cards. The complete physical (mechanical) and the environmental layers are retained as specified in the IEEE 1386 CMC ("Common Mezzanine Card") standard except as noted in this document. If the information in this document contradicts IEEE 1386 or IEEE 1386.1, this document takes precedence. Processor PMC cards are used where modular attachment of a processor is desired. These processor PMC cards may be used in conjunction with PMC I/O cards, traditional PCI cards, or with directly attached PCI components. As such, Processor PMCs increase the modularity of a computer system and thus complement, rather than compete with, the existing family of PMC cards. Processor PMC cards are expected to electrically operate with existing carrier boards (or motherboards); that is, while the carrier may be redesigned to take advantage of the enhanced functions that are offered by this standard, such a redesign should not be a requirement to insure proper operation. Indeed, Processor PMCs shall be specifically enabled to operate as master/host CPUs; otherwise, such cards revert to traditional PMC modes, operating as intelligent slave/target processor boards. As the PCI bus is extended to support faster CPUs and the systems that support them, PMCs and Processor PMCs will also evolve. Refer to the ANSI/VITA 39-2003 PCI-X Auxiliary Standard for details concerning support of PCI-X when that support is required within PMC and Processor PMC designs. |
Released |
| VITA 34 | A Scalable Modular Architecture for embedded applications in the military (COTS), telecommunications, industrial, and scientific marketplaces. | Specification addressing cooling, mechanicals, power, and protocol/software interoperability. The driving force for this activity is the need to provide better cooling methods and the move away from parallel bus architectures and towards high speed serial interconnects. This effort has been suspended in favor of activities in VXS and VPX. | Suspended |
| ANSI/VITA 35-2000 | Pin assignments for PMC P4 connector - Provides a mapping of PMC P4 to VME P0 and P2 connectors. | This standard provides pin mapping assignments between a PCI mezzanine Card (PMC) module's user IO connector (P4) and the VME host's user IO connector. Four mappings are provided. Other standards such as Compact PCI (CPCI) which supports a PMC and a VME-P0 style connector on the host could also use this standard. |
Released |
| VITA 36 | PMC I/O Modules | Specification to define I/O pinouts for various types of PMC I/O Modules. Refer to PICMG 2.15 for details on PTMC pinouts. | Suspended |
| ANSI/VITA 38-2003 | Intelligent Platform Management Interface (IPMI) with VME -This standard describes a methodology for using IPMI for System Management of VME systems. | This standard is based on the PICMG 2.9 System Management specification and describes the additional requirements for implementing Intelligent Platform Management Interface (IPMI) in a VME system. IPMI describes a hardware independent interface between chassis sensors and the operating system. IPMI is particularly useful for managing servers and High Availability systems. | Released |
| ANSI/VITA 39-2003 | PCI-X for PMC and Processor PMC - This standard integrates the PCI-X capability from PCI to PMC based products, including standard PMCs as well as Processor PMCs. | This standard integrates the PCI-X capability from PCI bus to PMC based products, including standard PMCs as well as Processor PMCs. PCI-X is defined in the PCI-X Addendum to the PCI Local Bus Specification and is the basis for the updates in this document.The physical (mechanical) and the environmental layers are specified in the IEEE 1386 CMC ("Common Mezzanine Card") and IEEE 1386.1 PMC ("PCI Mezzanine Card"). VITA 32 Processor PMC standard incorporates a set of extensions to IEEE 1386/1386.1 creating a new class of CPU based PMC cards. | Released |
| ANSI/VITA 40-2003 | Status Indicator Standard - This standard defines the colors, behaviors, placement, and labeling of service indicator lamps for boards, field replaceable units, and enclosures. | This standard defines the colors, behaviors, placement, and labeling of service indicator lamps for boards, field replaceable units, and enclosures. The purpose of this specification is to provide the information needed to design service indicators for boards, subsystems, and enclosures. This document describes a service indicator standard that seeks to be as compatible as possible with existing indicator standards and their extensions across different product markets. This standard addresses the meaning and application of specific colors to service indicators. This standard also defines and assigns meanings to specific approved behaviors or states for each color. It specifies where indicators must be placed and in what order, and it specifies luminance levels and viewing angles. |
Released |
| ANSI/VITA 41.0-2006 | VXS - VMEbus Switched Serial - This standard is the base standard defining physical features of VXS components, coupled with a set of protocol layer standards to define the specific serial interconnect used in a system implementation. | The VME Switched Serial (VXS) standard comprises this base standard defining physical features of VXS components, coupled with a set of protocol layer standards to define the specific serial interconnect used in a system implementation. The VXS base standard defines physical features that enable high-speed communication in a VME compatible system. These features include: addition of a high speed connector to the VME64x board in the P0/J0 position, a 6U by 160mm by 6HP Eurocard format board with many high speed connectors which may act as a switch, and the backplane/chassis infrastructure needed to support these features. In addition to defining a high -speed connector in the P0/J0 area, VXS also defines alignment and keying features which may be used to protect this and future alternate connectors. The ratio of one high-speed connector per payload board to many on the switch card lends itself to a star topology where each payload card is connected to a central switch. For higher reliability and/or load balancing, two switch cards may be used in a dual star configuration. Interswitch links may be included for reliability and load balancing reasons as well. Although this topology is not required it is a natural fit for the system features. |
Released |
| ANSI/VITA 41.1-2006 | VXS 4X InfiniBand™ Protocol Layer Standard | InfiniBand is a technology that was designed for both System-Area-Networking and clustering. Clustering is a method used to achieve high availability performance by combining two or more functional systems with redundancy in mind. (In effect, each functional system becomes a subsystem of the high availability system.) InfiniBand uses a point-to-point scaleable switched- fabric for its transport layer. Employing 2.5 gigabit per second bi-directional links as the 1X base, InfiniBand scales to higher bandwidths with 4X links and 12X links. In addition to simple networking, InfiniBand supports a low-processor-overhead distributed-computing message passing model. With its support of multiple connection protocols, good security features and variable sized packets, a robust system with excellent flexibility and performance is achieved. By pushing most of the protocol stack processing into silicon, InfiniBand is able to appear lightweight to the sub-systems that use it, even though the services provided by InfiniBand are comprehensive. The objectives of this document are:
The requirements and design rules defined in this standard are intended to be consistent with the applicable sections of the InfiniBand Specification. It is expected that VXS.1 products will comply with InfiniBand Signal, Link, Transport, and Management layers in order to maximize interoperability with other InfiniBand hardware and software products. |
Released |
| ANSI/VITA 41.2-2006 | VXS 4X Serial RapidIO™ Protocol Layer Standard | Serial RapidIO™ is a technology that was designed for both System-Area-Networking and clustering. Clustering is a method to achieve high availability performance by combining two or more functional systems with redundancy in mind. (In effect, each functional system becomes a subsystem of the high availability system.) Serial RapidIO uses a point-to-point scaleable switched-fabric for its transport layer. Employing 1.25, 2.5, or 3.125 Gigabit per second bi-directional links as the 1X base, Serial RapidIO scales with 4X links and 1X links (the 4X version is employed in this specification). Serial RapidIO technology is useful in applications where a simple memory mapped load-store access model is desired. The advantage of the load-store model includes much lower transaction overhead and lower resulting communication latency between processing elements as compared to message based interconnects The Serial RapidIO physical interface is compatible with a commodity backplane technology such as VXS. The transaction overhead is very low. Transaction transport is managed completely in hardware and error detection of the link protocol is robust. The objectives of this document are:
The guidelines and design rules defined in this standard are intended to be consistent with the applicable sections of the Serial RapidIO Specification. It is expected that VXS.2 products will comply with Serial RapidIO Signal, Link, Transport, and Management layers in order to maximize interoperability with other Serial RapidIO hardware and software products. |
Released |
| VITA 41.3 | VXS 1000Mb/s Baseband IEEE 802.3 Protocol Layer Standard | This standard defines an implementation of IEEE Std 802.3 within the VXS framework that provides 1Gb/s full-duplex data transfer over two differential pairs using 8B/10B encoding and baseband signaling. This implementation is based on 1000BaseCX as defined in IEEE Std 802.3- 2002, Clause 39, modified as described in Section 7 of this document. Within this standard, this signaling system is referred to as 1000Mb/s baseband IEEE 802.3 signaling. 1000Mb/s baseband IEEE 802.3 signaling is useful for both data and control planes in medium-performance applications that follow a packet-based communications model. The use of 1000Mb/s baseband IEEE 802.3 signaling is particularly attractive because of the wide range of readily available low-cost hardware and software that has been developed for it over time. The objectives of this document are:
The guidelines and design rules defined in this standard are intended to be consistent with the requirements of IEEE Std 802.3-2002. It is expected that VXS.3 products will comply with all the applicable clauses of IEEE Std 802.3-2002 to enable the use of standard hardware and software and maximize the potential for interconnection with other 1000Mb/s baseband IEEE 802.3 systems. |
Working Group |
| VITA 41.4 | VXS 4X PCI Express Protocol Layer Standard | PCI Express uses a point-to-point scaleable switched-fabric for its transport layer. Employing 2.5 gigabit per second bidirectional links as the 1X base, PCI Express scales with 2X, 4X, 8X, 12X, 16X and 32X links The 4X version is employed in this specification. PCI Express technology is useful in applications where a simple memory mapped load-store access model is desired. The advantage of the load-store model includes lower transaction overhead and lower resulting communication latency between processing elements as compared to message based interconnects. The objectives of this document are:
The requirements and design rules defined in this standard are intended to be consistent with the applicable sections of the PCI Express Specification. It is expected that VXS.4 products will comply with PCI Express Signal, Link, Transport, and Management layers in order to maximize interoperability with other PCI Express hardware and software products. |
Working Group |
| VITA 41.5 | VXS Aurora Protocol Layer Standard | This specification defines an open standard for supporting the Aurora point-to point interconnect protocol within the VXS architecture. In light of this objective, specific goals include:
The guidelines and design rules defined in this standard are intended to be consistent with the requirements of Aurora v1.3. It is expected that VXS.5 products will comply with all the applicable clauses of Aurora Specification v1.3 to enable the use of standard hardware and software and to maximize the potential for interconnection with other Aurora v1.3 systems. |
Working Group |
| VITA 41.6 | VXS 1X Gigabit Ethernet Control Channel Layer Standard | Working Group | |
| VITA 41.7 | Processor Mesh | This document is a proposal for the standardization of a higher performance redundant processor mesh topology designed to be used with the existing VITA 41.0 switch and payload board products. This 4x redundant fabric mesh is extremely flexible providing support for all major serial fabrics including Ethernet, Fiber Channel, InfiniBand™, Serial RapidIO™, and PCI Express it can be expected. The VITA 46.0 VMEbus Switched Serial Architecture also known as VXS was the first VMEbus technology to provide a central fabric architecture enabled by the new generation of high speed differential connectors. This new connector supports a much greater bandwidth than either the IEC 60602-3 or the IEC 61076-4-113 or the IEC 61076-4-101 connectors (known commonly as the DIN, 5-row DIN, and the 2mm Hard Metric connectors). The VXS processor mesh architecture is a new topology created to utilize existing VXS payload and switch cards. This new topology has all the standard features of a typical VXS backplane architecture. However, in addition, it has a bus segment of very high connectivity that has point-to-point links in a full redundant mesh topology. The slot definitions for this meshed segment of slots still conforms to the original switch slot as defined in VITA 41.0. It is only how the backplane routes the connections that are new. This meshed topology supports direct serdes-to-serdes communication which is particularly efficient and deterministic in comparison to the center switched fabric that is supported by the existing two fabric switch card. The principal features of this enhanced architecture are:
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Working Group |
| VITA 41.10 | VXS Live Insertion System Requirements | The design requirements in this standard permit Live Insertion compliant VITA 41 boards t o be removed from or inserted into powered and operating subracks. This document contains design requirements for 6U live insertable boards, backplanes, and systems that accomplish that feature. This standard is based upon the ANSI/VITA 1.1-1997 VME64 Extensions standard, and is complementary to the VITA 1.4-200x VME64x Live Insertion draft standard. This specification defines the requirements for live insertion of a VITA 41 switch board, or a payload board that doesn’t implement VME data signaling. A payload board that does implement the VME data signaling will have additional requirements as specified in VITA 1.4, especially those having to do with bus grant, interrupt grant, and LI/O signals. VITA 41.10 specifies hardware elements that are a superset of the ANSI/VITA 1.1-1997 VME64 Extensions Standard. |
Working Group |
| VITA 41.11 | VXS Payload Rear Transition Module Standard | The purpose of this specification is to define rear transition module connections for payload cards in a VXS chassis. Rear Transition Modules (RTM) provide the mechanism for providing industry standard connectors for on-board resources as a board designer confronts the limited amount of space on the front panel of a VME card. It also permits an improved cabling configuration by allowing some or all cabling from a board to be routed out the back of the chassis, thus providing unobstructed access to the faceplate. The number of slot positions that an RTM may cover in the rear is unrestricted as space at the rear of a rack is at less of a premium than that in the front (where the processing power resides). This permits a system architect to utilize rear panels that are wider than a single slot in order to provide a more robust attachment mechanism for cabling as well as the ability to use larger, or more, connectors than would be feasible on a VME card’s front panel alone. | Working Group |
| VITA 42.0 | XMC - This specification defines an open standard for supporting high-speed, switched interconnect protocols on PMC, an existing, widely deployed mezzanine form factor. | This specification defines an open standard for supporting high-speed, switched interconnect protocols on an existing, widely deployed form factor. In light of this objective, specific goals include supporting:
In support of these goals, this document specifies the mechanical and generic electrical requirements necessary to serve as a basis for any number of protocol layer standards built on and complying with this standard. The XMC Mezzanine Card base standard defines physical features that enable switched communications between a standard mezzanine card and its carrier. These features include the addition of one or more connectors carrying the additional electrical signals necessary for such communications. In addition to providing signals to carry data to and from the carrier module, these highspeed connectors provide adequate power, ground, and auxiliary signals so that the mezzanine card can function without signals from any standard PMC connectors, thus making PMC connectors optional. This specification requires no changes to existing PMC connectors, allowing them to continue supporting PCI-32 and PCI-64 protocol layers. This specification is currently designated as a "Draft Standard for Trial Use (DSTU)" under VITA's ANSI procedures and is NOT presently an American National Standard. |
Working Group |
| VITA 42.1 | XMC Parallel RapidIO 8/16 LP-LVDS Protocol Layer Standard | This specification defines an open standard for supporting Parallel RapidIO switched interconnect protocol on the XMC form factor. The objectives of this document are:
The guidelines and design rules defined in this standard are intended to be consistent with the applicable sections of the Parallel RapidIO Specification. It is expected that XMC.1 products will comply with Parallel RapidIO Physical, Transport, and Logical layers in order to maximize interoperability with other Parallel RapidIO hardware and software products. This protocol layer document builds upon the XMC.0 base standard by describing how XMC carriers and XMC mezzanine cards may communicate in a standard way using the Parallel RapidIO protocol. |
Working Group |
| VITA 42.2 | XMC Serial RapidIO Protocol Layer Standard | This specification defines an open standard for supporting the Serial RapidIO switched interconnect protocol on the XMC form factor. In light of this objective, specific goals include supporting:
The guidelines and design rules defined in this standard are intended to be consistent with the applicable sections of the Serial RapidIO specification. It is expected that XMC.2 products will comply with Serial RapidIO Physical, Transport, and Logical layers to realize maximum interoperability with other Serial RapidIO hardware and software. This protocol layer standard builds on the XMC base standard by describing how XMC carriers and XMC mezzanine cards may communicate in a standard way using the Serial RapidIO protocol. |
Working Group |
| VITA 42.3 | XMC PCI Express Protocol Layer Standard | This specification defines an open standard for supporting PCI Express switched interconnect protocol on the XMC form factor. The objectives of this document are:
This protocol layer standard builds on the XMC base standard by describing how XMC mezzanines communicate with XMC carriers in a standard way using the PCI Express interface standard. |
Working Group |
| VITA 42.4 | XMC HyperTransport Protocol Layer Standard | This specification defines an open standard for supporting Hyper Transport interconnect protocol on the XMC form factor. The objectives of this document are:
The overall objective of this specification is to detail the electrical implementation of the HyperTransport interface on the VITA 42.0 XMC form factor. This protocol layer standard builds on the XMC base standard by describing how XMC mezzanines communicate with XMC carriers in a standard way using the HyperTransport I/O technology. |
Working Group |
| VITA 42.10 | XMC General Purpose I/O Standard | XMC mezzanine products are anticipated to make use of a number of common secondary interfaces to the carrier in addition to the high-speed primary interconnect fabrics described in other parts of the VITA 42 specification suite. These interfaces typically provide local control interface functions for XMC resources, and may also serve as secondary conduits for data plane interconnect. The objective of this specification is to supplement the XMC base specification requirements defined within VITA 42.0, in order to provide consistent pin assignments for commonly used interfaces on the secondary XMC connectors (P16 and P26). These interface definitions are limited to signal assignments on the XMC connectors, and do not change the electrical or data format functional definitions associated with any of the protocols addressed by this specification. This specification provides no definitions for interface link wiring on the carrier board or through the host system. Interfaces defined in this specification include the following:
Other interface ports, such as I2C serial links or video ports, may also be carried on the XMC secondary connectors. The system designer is responsible for managing signal assignments for those ports, as those assignments are outside the scope of this specification. This application standard builds on the XMC base standard by describing how XMC mezzanines interface secondary functions on XMCs through the Secondary connectors P15 and P16. This document provides pin assignments and limited system application information. The reader is referred to applicable governing standards documentation for the various interfaces described in this specification for full interface requirements. |
Working Group |
| VITA 43S | Hot Swap NexGen Mezzanine | Suspended | |
| VITA 45S | Serial VME | Cancelled | |
| VITA 46.0 | VPX - This specification defines an open standard for supporting high-speed, switched interconnect protocols on 3U and 6U IEEE1101 form factors with a new connector scheme. | Commonly known as VPX, this specification family defines entirely new high-speed connectors in part to carry mappings for popular switched serial fabrics including Gigabit Ethernet, PCI Express, Serial RapidIO, InfiniBand, and Aurora. It also defines a new increased power envelope including a 48V profile, and additional cooling methods. The base standard does not address the possible serial fabric configurations available in systems which utilize the standard. This specification is NOT presently an American National Standard. |
Working Group |
| VITA 46.1 | VPX VMEbus Signal Mapping | This standard is one of the “dot” specifications within the VITA 46 family of specifications. It defines the mapping of VMEbus signals to the standard. The objective of this specification is to supplement the VITA 46 base specification with the definition for the VMEbus signals as mapped to a VITA46 connector. |
Working Group |
| VITA 46.2 | VPX PCI bus | This standard is one of the “dot” specifications within the VITA 46 family of specifications. It defines the mapping of PCI bus signals to the standard. The objective of this specification is to supplement the VITA 46 base specification with the definition for the PCI bus signals as mapped to a VITA46 connector. |
Working Group |
| VITA 46.3 | VPX 4x Serial RapidIO Signal Mapping | This standard is one of the “dot” specifications within the VITA 46 family of specifications. It defines the mapping of Serial Rapid IO signals to the standard. The objectives of this document are:
The guidelines and design rules defined in this standard are intended to be consistent with the applicable sections of the Serial RapidIO Specification. It is expected that VITA 46.3 products will comply with Serial RapidIO Signal, Link, Transport, and Management layers in order to maximize interoperability with other Serial RapidIO hardware and software products. |
Working Group |
| VITA 46.4 | VPX PCI Express | This document defines the implementation of PCI Express technology for VITA-46 backplanes. | Working Group |
| VITA 46.5 | VPX HyperTransport | This document defines the implementation of HyperTransport™ technology for VITA-46 backplanes. The objectives of this document are:
The guidelines and design rules defined in this standard are intended to be consistent with the requirements of HyperTransport I/O Link Specification Rev. 2.0, and VITA-46 requirements. It is expected that HyperTransport VITA-46 products will comply with all the applicable clauses of HyperTransport I/O Link Specification Rev. 2.0 to enable the use of standard hardware and software and maximize the potential for interconnection with other HyperTransport modules. |
Working Group |
| VITA 46.6 | VPX Gbit Ethernet | This document defines the implementation of Gbit Ethernet technology for VITA-46 backplanes. | Working Group |
| VITA 46.7 | VPX 10Gbit Ethernet | This document defines the implementation of 10 Gbit Ethernet technology for VITA-46 backplanes. | Working Group |
| VITA 46.8 | VPX Infiniband | This document defines the implementation of Infiniband technology for VITA-46 backplanes. | Working Group |
| VITA 46.9 | VPX PMC/XMC Pinout Mapping | The objective of this specification is to supplement the VITA 46.0 base specification requirements in order to fully define the User I/O signal mapping between the pins of PMC and/or XMC card sites provided on a VITA 46-compliant carrier. Because of the numerous possibilities presented by combinations of 3U and 6U VITA46 carriers supporting single or dual width PMC and/or XMC mezzanines it is impractical to provide a fully comprehensive specification. Therefore, this standard will cover only the following combinations, which have been determined the most likely to be actually implemented in practice:
The overall objective of this specification is to detail the connection mapping between the defined mezzanine connector contact position and the associated backplane (BP) connector contact position for the above detailed combinations. |
Working Group |
| VITA 46.10 | VPX Rear Transition Module | The objectives of this standard are:
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Working Group |
| VITA 46.12 | VPX Keying Definitions Plug-In Modules and Backplanes | Working Group | |
| VITA 46.13 | VPX Power Sequencing and System Management | Working Group | |
| ANSI/VITA 47-2005 | Environmental, Design and Construction, Safety, and Quality for Plug-In Units Standard - This standard defines environmental, design and construction, safety, and quality requirements for commercial-off-the-shelf (COTS) plug-in units (cards, modules, etc) intended for mobile applications. | This standard defines environmental, design and construction, safety, and quality requirements for commercial-off-the-shelf (COTS) plug-in units (cards, modules, etc) intended for mobile applications. COTS plug-in units are widely used in commercial and military, ground and aerospace, mobile applications. Certification of COTS plug-in units, by supplying vendors, to this standard will facilitate the cost effective integration of these items in larger systems. | Released |
| VITA 48.0 | REDI (Ruggedized Enhanced Design Implementation) | This standard defines a general mechanical design implementation for circuit card assemblies that will enhance both their thermal performance and structural integrity as well as provide 2 level maintenance compatibility. This standard will give an overview of the associated plug-in units for air-cooling, conduction cooling, and liquid flow thru and spray cooling applications. Specific connector-mounting details are defined in VITA 46. The VITA 48 family of standards will define applicable detailed dimensions of key module and sub-rack interfaces. The implementations described in this standard are targeted for 3U and 6U form factor boards on 0.85 and 1.00 centers. However, the packaging approach presented is applicable to boards with other form factors, different connector series and can accommodate alternate module pitches. The purpose of this standard is to define an overall approach to packaging modules to improve both their thermal and structural characteristics as well as incorporate the provisions for 2 level maintenance. In addition this standard will define the applicable environmental requirements of plug-in units to ensure successful integration into higher levels of assembly. |
Working Group |
| VITA 48.1 | Mechanical Specifications for Microcomputers Using REDI Air Cooling Applied to VITA 46 |
This standard defines an implementation of VITA 48.0 applied to boards/modules defined in VITA 46. This standard will give the dimensions of associated plug-in units for air-cooling applications and connector-mounting details together with applicable detail dimensions of key sub-rack interfaces. The module assemblies defined by this standard will be compatible with two level maintenance applications. The purpose of this standard is to specify the critical dimensions that will ensure the mechanical interchangeability of plug-in modules for air cooling applications. |
Working Group |
| VITA 48.2 | Mechanical Specifications for Microcomputers Using REDI Conduction Cooling Applied to VITA 46 |
This standard defines an implementation of VITA 48.0 applied to boards/modules defined in VITA 46. This standard will give the dimensions of associated plug-in units for conduction cooling applications and connector-mounting details together with applicable detail dimensions of key sub-rack interfaces. The module assemblies defined by this standard will be compatible with two level maintenance applications. The purpose of this standard is to specify the critical dimensions that will ensure the mechanical interchangeability of conduction cooled plug-in modules. |
Working Group |
| VITA 48.3 | Mechanical Specifications for Microcomputers Using REDI Liquid Cooling Applied to VITA 46 |
This standard defines liquid cooling implementations of VITA 48.0 applied to boards/modules defined in VITA 46. This standard will give the dimensions of associated plug-in units for liquid cooling applications and connector-mounting details together with applicable detail dimensions of key sub-rack interfaces. The module assemblies defined by this standard will be compatible with two level maintenance applications. The purpose of this standard is to specify the critical dimensions that will ensure the mechanical interchangeability of plug-in modules for liquid cooling implementations addressed in this standard. |
Working Group |
| VITA 49.0 | Digital Intermediate Frequency (IF) | Many communication systems route information using proprietary analog IF, digital IF, and processed digital information. VITA-49.0 unifies these methods by specifying a method to transfer digitized signal data and metadata. This method describes signals on a time-accurate basis and includes other signal context information important to RF applications. | Working Group |
| VITA 50 | Electronic Module Cooling Best Practices | This standard provides an overview of demonstrated electronics cooling methods. While it is targeted specifically to electronics cooling, the cooling systems and components described can be applied to any device or enclosure that requires cooling. | Working Group |
| VITA 51.0 | Reliability Prediction | This document provides guidance on best practices for reliability assurance activities that will improve the reliability of electronic modules. It addresses the limitations of existing prediction practices, with an initial focus on creating a daughter standard for the use of MIL-HDBK-217. | Working Group |
| VITA 51.1 | Reliability Prediction MIL-HDBK-217 Daughter Standard | This guide provides a standard method of performing reliability predictions on COTS modules using MIL-HDBK-217F Notice 2 stress analysis methodology. This is not a revision or a modification of MIL-HDBK-217F Notice 2 but a standardization of the inputs to the MIL-HDBK-217F Notice 2 calculations to give more consistent MTBF numbers. This guide will assist the user in determining the credibility of published failure rate information and outline the techniques necessary for developing and applying this information to military applications. | Working Group |
| VITA 52 | Lead Free Practices | Document to describe best practices to minimize or eliminate the effects of lead free manufacturing. | Study Group |
| VITA 53 | Commercial Technology Market Surveillance | This standard describes VITA 53.0 Commercial Technology Market Surveillance, defining the types of market surveillance data needed by Department of Defense program managers in order to develop and implement technology refresh plans. Technology refresh events are fueling the large majority of new DoD acquisition efforts in the post-"Perry memo" era of increased DoD reliance on commercial technology vendor design, production, support, and repair services. | Study Group |
| VITA 54 | EPMA (Embedded Platform Management Architecture) | For Platform Management, this standard defines a physical backplane interface and a pluggable management module suitable for use on commercial and ruggedized circuit card assemblies. | Working Group |
| VITA 55.0 | Aurora on VME | This specification defines an open standard for a point-to-point transport layer protocol suitable for use between FPGA-endpoints. Specific goals include:
In support of the above goals the VITA-55.0 standard comprises this base standard defining the transport layer only. Other standards within the VITA-55.x family will define how this transport layer should interface to common link layer components. |
Working Group |
| VITA 56.0 | EMC (Express Mezzanine Card) Base Standard | The Express Mezzanine Card (EMC) specification defines the base-level requirements for a wide-range of high-speed mezzanine cards optimized for, but not limited to, 6U CompactPCI and VME Host boards. This base specification defines the common elements for each implementation including mechanical, management, power, thermal, and interconnect. Subsidiary specifications will define the usage requirements for each interface implementation. Target interfaces include PCI Express, Advanced Switching, Serial RapidIO, and Gigabit Ethernet. | Working Group |
| VITA 56.1 | EMC PCI Express | This subsidiary specification defines the operation of PCI Express interface ports on the EMC. As outlined in the EMC base specification (VITA 56.0), the EMC may have two sets of PCI Express ports:
These ports are wired per the physical layer signal path requirements of the PCI Express Base Specification (Rev 1.1) and the PCI Express Card Electromechanical Specification (Rev 1.1). In addition to the PCI Express serial ports, this document defines optional support for a 100 MHz reference clock for the PCI Express root controller on the EMC. This reference clock is utilized by the PCI Express controller to implement spread-spectrum clocking, as defined in the PCI Express CEM document. |
Working Group |
| VITA 56.2 | EMC Ethernet | This subsidiary specification defines the operation of Ethernet interface ports on the EMC. As outlined in the EMC base specification (VITA 56.0), the EMC may have two sets of Ethernet ports:
These ports are wired per the physical layer signal path requirements of the IEEE 802.3-2002 specification. This specification does specifically define operation of 10 Gigabit Ethernet ports beyond providing a definition for 4x Gig Ethernet port wiring in the “Fat Pipe” region, which could be amalgamated to provide 10 Gig Ethernet XAUI interface functions. |
Working Group |
| VITA 56.4 | EMC Serial Rapid IO | This subsidiary specification defines the operation of Serial Rapid IO (SRIO) interface ports on the EMC. As outlined in the EMC base specification (VITA 56.0), the EMC may have one or more dataplane or application traffic SRIO ports in the “Fat Pipes” port group. Each of these ports are implemented using the full rate, Short Reach electrical interface definitions, and may be implemented in x1, x2, or x4 configurations. These ports are wired per the physical layer signal path requirements of the Serial Rapid IO Interconnect Specification. | Working Group |
| VITA 56.10 | EMC Conduction Cooled Packaging | This subsidiary specification provides detailed implementation requirements for EMCs packaged for passive conduction-cooled carrier and chassis environments. | Working Group |
| VITA 56.20 | EMC General Purpose Interfaces | This subsidiary specification will define recommended configurations of common general purpose I/O ports at the Common Options port field on the EMC carrier connector. These ports typically provide local interfaces to the carrier or host systems to support secondary messaging or local storage access. Interfaces to be documented in this specification include:
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Working Group |
| VITA 57 | Mezzanine Standard for FPGA IO | This standard describes VITA 57 IO Mezzanine Modules for VMEbus Systems. This standard introduces a methodology that shall allow the front panel IO of IEEE 1101 form factor cards to be configured, via mezzanine boards. | Working Group |
| VITA 58 | Electronic Module Standardization | Defines a form factor standard for ruggedized electronic modules. | Working Group |
