VME2eSST
VME32 was conceived as an asynchronous bus, with a master placing data on the bus and waiting for an acknowledge from the slave before proceeding. In order to achieve greater bandwidth, it was felt a synchronous protocol was needed. Research was started on a synchronous protocol called VME320 which was first demonstrated in 1997. Using a proprietary backplane and a synchronously clocked data transfer, VME320 showed the technical merits of a synchronous protocol.
The VITA Standards Organization set out to improve on this research, with a key goal being use of standard unmodified VME32/64 backplanes (unlike VME320's proprietary backplane design). With some modifications and further improvements, the new 2eSST protocol was approved in ANSI/VITA 1.5 in 1999.
Data:
parallel, 64-bit
Bandwidth:
up to 320MB/sec
Please read:
2eSST VME Eases Design of Network-Centric Embedded Systems
ANSI/VITA 1.5 extends performance by adding dual edge, source synchronous data transfer (2eSST) capability that allows sustained data transfers in excess of 300MB/sec. The 2eSST protocol, is based on the asynchronous 2eVME protocol. The main exception to this is that during its data phases, 2eSST is a source synchronous protocol. No acknowledgment is expected from the receiver of the data. Hence, the theoretical performance of 2eSST is limited only by the skew between receiver and transmitter of data. Like 2eVME it uses incident wave switching to guarantee fast switching times and minimize skew. The result is a protocol that as currently defined doubles the theoretical bandwidth of VME to 320Mbytes/sec. The protocol can be broken into three main phases: address broadcast, data phase and termination.
- The address broadcast phase for 2eSST is identical to the address broadcast phase for 2eVME. However, the data phase is synchronous rather than asynchronous.
- VME32 utilizes a handshake protocol whereby data strobes (DS1* and DS0*) are acknowledged by DTACK* which then allows the data strobes to be removed which in turn allows the DTACK* to be removed. Once DTACK* is deasserted, a new cycle can begin.
- VME32 protocol requires four delays through the drivers, backplane and receivers plus the settling time of the backplane. 2eVME protocol improves upon this by using both edges of DS1*, DS0*, and DTACK* to qualify data. Throughput is doubled, but performance is still limited by the requirement for acknowledgment from the receiver of data.
In contrast, after the address phase, the 2eSST protocol sends the data and strobe and does not wait for any acknowledgments. Therefore, data can be sent at much higher bandwidth. Both edges of the strobe are used: falling edge for odd data beats and rising edge for even data beats.
Thales Computers designed the Alma2e bridge supporting the 2eSST protocol in 2002. Tundra Semiconductor, working with Motorola, brought the Tsi148 PCI/X-to-VME2eSST bridge to market in 2004, making the 2eSST protocol available to the entire industry. Concepts exist to enhance VME2eSST that could increase performance further to over 1GB/sec.
