TEK MICROSYSTEMS

TEK Microsystems' Web Site

TEK Microsystems
2 Elizabeth Drive
Chelmsford MA 01824, USA
Telephone: (978) 244-9200
Fax: (978) 244-1-78
Email: info@tekmicro.com
http://www.tekmicro.com

TEK Microsystems develops and manufactures high-performance VME, VME64, VSB, RACEway, FastPack IP, and FastPMC modules which support data acquisition, control, and instrumentation applications. Supported interfaces include general purpose I/O, parallel I/O, serial I/O, fiber optic, and high-speed digital instrumentation recorders such as the Ampex DCRsi family. TEK also develops custom hardware modules and provides software development and integration services.

Processor Boards

Processor Type Description Software
Support ADDR/
DATA
Width Size

Dual PMC
Dual PowerPC
Carrier Dual PMC I/O subsystems for VME/RACEway. Local PowerPC 8245 CPU for each PMC, 64-bit 33 MHz PCI, EIA-232, FLASH, 128-256 MB SDRAM, Fast Ethernet. Onboard RACE++ fabric, quad 128-256 MB SDRAM memory buffers, dual port RACEway/RACE++ interface on P2. 500 MB/s I/O bandwidth in a single VME slot. Model No. PowerRACE-2B . . 6U

Dual PMC
Dual PowerPC
FPGA I/O
Processor Dual PMC I/O subsystems for VME/RACEway. Local 440GX PowerPC for each PMC, 64-bit 33-50 MHz PCI. Dual Xilinx Virtex II Pro VP30 FPGAs with 2 onboard 405 PPCs, reconfigurable for application-specific functions. EIA-232, Bulk FLASH, 128-256 MB SDRAM, Gigabit Ethernet. Onboard RACE++ fabric, 128-256 MB DDR memory buffers, dual port RACEway/RACE++ interface on P2. 500 MB/s I/O bandwidth in a single VME slot. Model No. PowerRACE-3 . . 6U

Processor Type	Description	Software Support	ADDR/ DATA Width	Size
Dual PMC Dual PowerPC Carrier	Dual PMC I/O subsystems for VME/RACEway. Local PowerPC 8245 CPU for each PMC, 64-bit 33 MHz PCI, EIA-232, FLASH, 128-256 MB SDRAM, Fast Ethernet. Onboard RACE++ fabric, quad 128-256 MB SDRAM memory buffers, dual port RACEway/RACE++ interface on P2. 500 MB/s I/O bandwidth in a single VME slot. Model No. PowerRACE-2B	.	.	6U
Dual PMC Dual PowerPC FPGA I/O Processor	Dual PMC I/O subsystems for VME/RACEway. Local 440GX PowerPC for each PMC, 64-bit 33-50 MHz PCI. Dual Xilinx Virtex II Pro VP30 FPGAs with 2 onboard 405 PPCs, reconfigurable for application-specific functions. EIA-232, Bulk FLASH, 128-256 MB SDRAM, Gigabit Ethernet. Onboard RACE++ fabric, 128-256 MB DDR memory buffers, dual port RACEway/RACE++ interface on P2. 500 MB/s I/O bandwidth in a single VME slot. Model No. PowerRACE-3	.	.	6U

Backplanes

Configuration Description Size

RACEway Test Adapter used to implement a single-port, 2-slot RACEway interconnect between two ANSI/VITA 5-1994 RACEway cards. Designed for use in laboratory or test environments for evaluation of RACEway cards. The single port adapter may be used with both 3-row and 5-row P2 connectors. Model No. RTA-S-2 3U

RACEway Test Adapter used to implement a dual-port, 2-slot RACEway interconnect between two dual-port ANSI/VITA 5.1-1994 RACEway cards. Designed for use in laboratory or test environments for evaluation of RACEway cards. The dual-port adapter may also be used for single port interfaces provided that the VMEbus backplane has 5-row P2 connectors. Model No. RTA-D-2 3U

Configuration	Description	Size
RACEway	Test Adapter used to implement a single-port, 2-slot RACEway interconnect between two ANSI/VITA 5-1994 RACEway cards. Designed for use in laboratory or test environments for evaluation of RACEway cards. The single port adapter may be used with both 3-row and 5-row P2 connectors. Model No. RTA-S-2	3U
RACEway	Test Adapter used to implement a dual-port, 2-slot RACEway interconnect between two dual-port ANSI/VITA 5.1-1994 RACEway cards. Designed for use in laboratory or test environments for evaluation of RACEway cards. The dual-port adapter may also be used for single port interfaces provided that the VMEbus backplane has 5-row P2 connectors. Model No. RTA-D-2	3U

PMC Modules

Function Description

Front Panel
Data Port
Interface ANSI/VITA 17 Front Panel Data Port (FPDP) interface, software programmable selection of FPDP/TM, /R, or /RM. TTL and PECL STROBE support, 32-bit PMC bus @33MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-FPDP

Customizable
EIA-485 or
TTL I/O Customizable EIA-485 or TTL I/O, implements up to 32 EIA-485 I/O signals or 64 TTL I/O signals. 32-bit PMC bus @33 MHz,132 MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-DFLEX64

EIA-485
Parallel
Data Flexible, high performance parallel EIA-485 data transfer. Two independent 16-bit parallel interfaces, each of which can be configured for input or output under software control. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, variable word width, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-PDIO32

LVDSChannel Link
Input
(EIA-644) Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has two DS90CR286 28-bit interfaces and supports burst data rates up to 1.848 Gbps per 28-bit channel. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVI-2x28

LVDSChannel Link
Input
(EIA-644) Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has three DS90CR484 48-bit (36 bits utilized) interfaces for burst data rates up to 4.032 Gbps. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVI-3x36

LVDSChannel Link
Output
(EIA-644) Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has two DS90CR285 28-bit interfaces and supports burst data rates up to 1.848 Gbps per 28-bit channel. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVO-2x28

LVDSChannel Link
Output
(EIA-644) Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has three DS90CR484 48-bit (36 bits utilized) interfaces for burst data rates up to 4.032 Gbps. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVO-3x36

Parallel
ECL/PECL
Input Flexible, high performance parallel ECL/PECL input solution. 32-bit PMC bus @33MHz, 132MB/s data transfer, customizable FPGA, variable word width, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-PEI32

Parallel
ECL/PECL
Output Flexible, high performance parallel ECL/PECL output solution. 32-bit PMC bus @33MHz, 132MB/s data transfer, customizable FPGA, variable word width, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-PEO32

Full-duplex
Dual
Fiber Optic
I/O Module 0-26.6 MB/sec. uses Cypress HOTLink encoder/decoders, supports two separate 400 Mbps input streams and two separate 400 Mbps output streams. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-2HL400

Full-duplex
Fiber Optic
I/O Module 0-26.6MB/sec. Uses Cypress HOTLink encoder/decoder, up to 266 Mbps using SC fiber connectors and 330 Mbps using copper media. 32-bit PMC bus @ 33MHz, 132MB/sec data transfer, 4KB FIFO for efficient DMA burst performance. Model No. FPMC-HL266

Full-duplex
2-Channel
Fiber Optic
I/O Module 60-400 Mbps. Uses Cypress HOTLink encoder/decoder, up to 400 Mbps using copper or fiber media. 32-bit @ 33 MHz PCI standard, 132 MB/sec data transfer. 64-bit 33 MHz PCI special order. 1 MB FIFO for efficient DMA burst performance. VxWorks drivers. Model No. FPMC-2HL400

Full-duplex
2-Channel
Fiber Optic
I/O Module 200 Mbps - 1.25 Gbps. Uses Cypress HOTLink encoder/decoder, with copper or fiber media. 64-bit PMC bus @ 66 MHz, 267 MB/s sustained data transfer, dual-port synchronous SRAM buffering. VxWorks drivers. Model No. FPMC-2HL1500

Full-Duplex
Fiber Optic
TAXI Interface 50-200 Mbps. Uses Cypress TAXI compatible HOTLink encoder/decoder, up to 200 Mbps using copper or fiber media. 32-bit PMC bus @ 33 MHz, 132 MB/s data transfer, customizable FPGA, 1 MB FIFO memory for efficient DMA burst performance. VxWorks drivers. Model No. FPMC-TAXI200

RACEway
Interface RACEway/RACE++ to PCI interface. Supports RACE 1.0 and RACE++ as Master or Slave. Maps RACEway mailbox events to PCI interrupts. Linked-list DMA controller. VxWorks driver software. Model No. RACEbridge-PMC

Function	Description
Front Panel Data Port Interface	ANSI/VITA 17 Front Panel Data Port (FPDP) interface, software programmable selection of FPDP/TM, /R, or /RM. TTL and PECL STROBE support, 32-bit PMC bus @33MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-FPDP
Customizable EIA-485 or TTL I/O	Customizable EIA-485 or TTL I/O, implements up to 32 EIA-485 I/O signals or 64 TTL I/O signals. 32-bit PMC bus @33 MHz,132 MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-DFLEX64
EIA-485 Parallel Data	Flexible, high performance parallel EIA-485 data transfer. Two independent 16-bit parallel interfaces, each of which can be configured for input or output under software control. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, variable word width, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-PDIO32
LVDSChannel Link Input (EIA-644)	Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has two DS90CR286 28-bit interfaces and supports burst data rates up to 1.848 Gbps per 28-bit channel. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVI-2x28
LVDSChannel Link Input (EIA-644)	Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has three DS90CR484 48-bit (36 bits utilized) interfaces for burst data rates up to 4.032 Gbps. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVI-3x36
LVDSChannel Link Output (EIA-644)	Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has two DS90CR285 28-bit interfaces and supports burst data rates up to 1.848 Gbps per 28-bit channel. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVO-2x28
LVDSChannel Link Output (EIA-644)	Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has three DS90CR484 48-bit (36 bits utilized) interfaces for burst data rates up to 4.032 Gbps. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVO-3x36
Parallel ECL/PECL Input	Flexible, high performance parallel ECL/PECL input solution. 32-bit PMC bus @33MHz, 132MB/s data transfer, customizable FPGA, variable word width, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-PEI32
Parallel ECL/PECL Output	Flexible, high performance parallel ECL/PECL output solution. 32-bit PMC bus @33MHz, 132MB/s data transfer, customizable FPGA, variable word width, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-PEO32
Full-duplex Dual Fiber Optic I/O Module	0-26.6 MB/sec. uses Cypress HOTLink encoder/decoders, supports two separate 400 Mbps input streams and two separate 400 Mbps output streams. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-2HL400
Full-duplex Fiber Optic I/O Module	0-26.6MB/sec. Uses Cypress HOTLink encoder/decoder, up to 266 Mbps using SC fiber connectors and 330 Mbps using copper media. 32-bit PMC bus @ 33MHz, 132MB/sec data transfer, 4KB FIFO for efficient DMA burst performance. Model No. FPMC-HL266
Full-duplex 2-Channel Fiber Optic I/O Module	60-400 Mbps. Uses Cypress HOTLink encoder/decoder, up to 400 Mbps using copper or fiber media. 32-bit @ 33 MHz PCI standard, 132 MB/sec data transfer. 64-bit 33 MHz PCI special order. 1 MB FIFO for efficient DMA burst performance. VxWorks drivers. Model No. FPMC-2HL400
Full-duplex 2-Channel Fiber Optic I/O Module	200 Mbps - 1.25 Gbps. Uses Cypress HOTLink encoder/decoder, with copper or fiber media. 64-bit PMC bus @ 66 MHz, 267 MB/s sustained data transfer, dual-port synchronous SRAM buffering. VxWorks drivers. Model No. FPMC-2HL1500
Full-Duplex Fiber Optic TAXI Interface	50-200 Mbps. Uses Cypress TAXI compatible HOTLink encoder/decoder, up to 200 Mbps using copper or fiber media. 32-bit PMC bus @ 33 MHz, 132 MB/s data transfer, customizable FPGA, 1 MB FIFO memory for efficient DMA burst performance. VxWorks drivers. Model No. FPMC-TAXI200
RACEway Interface	RACEway/RACE++ to PCI interface. Supports RACE 1.0 and RACE++ as Master or Slave. Maps RACEway mailbox events to PCI interrupts. Linked-list DMA controller. VxWorks driver software. Model No. RACEbridge-PMC

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