Acromag, Inc. Tel: (248) 295-0310
| Function | Description |
|---|---|
Digital Input/Output | 0-60V DC input range; Low-side output switches; outputs sink up to 1A per channel; change-of-state and level interrupts (up to 8 channels); TTL-compatible input threshold with hysteresis, -40° to 85°C option. Model No. PMC408 |
with Counter/Timers | 24 differential I/O, 16 TTL I/O, four 16-bit counter/timer channels with change of state and level interrupts, front or rear I/O access, -40° to 85°C option. Model No. PMC424 |
with Counter/Timers | 64 TTL I/O, four 16-bit counter/timer channels with change of state and level interrupts, front or rear I/O access, -40° to 85°C option. Model No. PMC464 |
| Ten 16-bit TTL counter/timers, waveform generation, frequency/period/pulse-width measurement, quadrature, interrupts, -40° to 85°C option. Model No. PMC482 | |
Quadrature TTL/RS422 | Four 16-bit TTL timer/counters and four 32-bit RS422 counter/timers. Model No. PMC483 |
Quadrature RS422 | Six 32-bit RS422 counter/timers. Model No. PMC484 |
| : Xilinx Virtex-II FPGA with 6,912 logic cells, 64 bi-directional TTL I/O lines, -40° to 85°C option. Model No. PMCDX501 | |
| Xilinx Virtex-II FPGA with 24,192 logic cells, 64 bi-directional TTL I/O lines, -40° to 85°C option. Model No. PMCDX2001 | |
| Xilinx Virtex-II FPGA with 6,912 logic cells, 32 differential RS422 I/O lines, -40° to 85°C option. Model No. PMCDX502 | |
| Xilinx Virtex-II FPGA with 24,192 logic cells, 32 differential RS422 I/O lines, -40° to 85°C option. Model No. PMCDX2002 | |
| Xilinx Virtex-II FPGA with 6,912 logic cells, 16 TTL and 24 differential RS422 I/O lines, -40° to 85°C option. Model No. PMCDX503 | |
| Xilinx Virtex-II FPGA with 24,192 logic cells, 16 TTL and 24 differential RS422 I/O lines, -40° to 85°C option. Model No. PMCDX2003 | |
| Xilinx Virtex-II FPGA with 6,912 logic cells, 32 LVDS I/O lines, -40° to 85°C option. Model No. PMCDX504 | |
| Xilinx Virtex-II FPGA with 24,192 logic cells, 32 LVDS I/O lines, -40° to 85°C option. Model No. PMCDX2004 | |
| Virtex-4 FPGA with 41,472 logic cells, plug-in I/O modules are available for front mezzanine, conduction cooled or 0 to 70°C operating range. Model No. PMC-LX40 | |
| Virtex-4 FPGA with 59,904 logic cells, plug-in I/O modules are available for front mezzanine, conduction cooled or 0 to 70°C operating range. Model No. PMC-LX60 | |
| LVDS and plug-In I/O modules, customizable FPGA with up to 34K logic cells and 192 XtremeDSP slices. Model No. PMC-SX35 |
CES-Creative Electronic Systems Tel: +41.22.884.51.00
| Function | Description |
|---|---|
I/O | User-programmable general purpose I/O PMC. User-programmable front-end 10 / 100 KGates FPGA to easilly integrate custom protocols and functions. Model No. GPIO 8405 |
| GPIO-based 64-bit TTL I/O PMC. Reprogrammable front-end FPGA. Model No. TTL 5205 | |
Differential I/O | GPIO-based 32-bit TTL Differential I/O PMC. RS-485/RS-422 lines PMC. Reprogrammable front-end FPGA. Model No. DIO 5252 |
Echotek Corporation Tel: (256) 721-1911
| Function | Description |
|---|---|
| Implements bidirectional Front Panel Data Port (FPDP Specification - ANSI/VITA 17-1998). Model No. FPDP-PMC |
ESD Tel: (800) 732-8006, +49 511-37 29 80
| Function | Description |
|---|---|
High Speed Inputs 16 Digital In 8 Digital Out | 2 FIFO ports with 16 bits width for TTL level. FIFO can be 4k or 16k. Max transfer rates: FIFO write via P1: 10Mhz; Read FIFO via PCI: 4MB/s. Interrupts at empty, half-full, full. Drivers for OS-9, VxWorks. Model No. PMC-FIFO |
General Standards Corporation Tel: (256) 880-8787
| Function | Description |
|---|---|
| Fast, flexible, and bi-directional. Transmits/receives data up to 80MB or up to 200MB/sec. Capable of transferring data to/from host memory using D32 block transfers, while FIFO memory provides continuous transmission of data. 7 bi-directional programmable handshake lines and eight pre-configured software selectable interface protocols allow easy interfacing to most I/O peripherals. Model No. PMC-HPDI32A | |
Change of State | 32-bit parallel digital input board that samples input data at selectable rates. Can detect any change-of-state and store the changed data word data in the on-board FIFO. Can be used in type mode by storing up to 64,000 samples after receipt of a trigger word. Model No. PMC-HPDI32A-COS |
| Flexible bi-directional 32-bit digital I/ O, transmits and receives data from 20 Mbytes (TTL I/ O) to 100 Mbytes/s (LVDS). Useful as a general-purpose DMA interface to a variety of external peripherals. PMC DMA engine capable of transferring data to/ from Host memory using D32 block transfers, FIFO memory (up to 1 Mbyte total FIFO) provides continuous transmission of data without interrupting tDMA transfers or requiring intervention from Host CPU. 7 bi-directional programmable handshake lines, 8 preconfigured software selectable interface protocols allow easy interfacing to most digital I/ O peripherals. Model No. PMC-HPDI32A-MULTI-I/O |
Pentek, Inc. Tel: (201) 818-5900
| Function | Description |
|---|---|
Multiband Digital Receiver | Two 80 or 105MHz, 14-bit A/D converters; 16 channels multiband digital receivers; 5 to 10MHz output; user-configurable Virtex-II FPGA; front-panel clock and sync bus; custom FPGA I/O; opt Pentek GateFlow FPGA design kit/IP Core Lib; ruggedized version available. Model No. 7131 |
Digital Upconverter/ Downconverter | Complete software radio transceiver; two 80 or 105 MHz A/Ds; VITA 42.0 XMC compatible; Virtex-II Pro FPGA for custom signal processing; multiboard synchronization; ruggedized and conduction-cooled version available. Model No. 7140 |
Digital Upconverter/ Downconverter | Complete software radio transceiver; two 105MHz A/Ds; VITA 42.0 XMC compatible with wideband dual digital downconverter core implemented in Virtex-II Pro FPGA; ruggedized and conduction-cooled version available. Model No. 7140-421 |
Digital Upconverter/ Downconverter | Complete software radio transceiver; two 105MHz A/Ds; VITA 42.0 XMC compatible with 256-channel narrowband digital downconverter core implemented in Virtex-II Pro FPGA; ruggedized and conduction-cooled version available. Model No. 7140-430 |
| Four 125 MHz 14-bit A/Ds; one digital upconverter with 500 MHz 16-bit D/A converter; 768 MB of DDR2 SDRAM; two Virtex-4 FPGAs; complete sofware radio interface solution; ruggedized and conductioncooled versions available. Model No. 7142 | |
| Two 125 MHz 14-bit A/Ds; four digital downconverters; one digital upconverter; two 500 MHz 16-bit D/A converters; 512 MB of DDR SDRAM; one Xilinx Virtex-II Pro FPGA; complete software radio PMC/XMC interface solution; conduction-cooled. Model No. 7141-703 |
Radstone Embedded Computing Tel: (800) 368-2738, +44 (0) 1327-359444
| Function | Description |
|---|---|
Module | Provides 32 channels arranged as 4 banks each of 8 channels. Various factory-fitted options are possible from 8 channels TTL/RS422 I/O, 8 channels TTL/RS422 I/O, 8 channels solid state relay/open collector, 8 channels solid state relay/open collector. Model No. PMC PIO1 |
SBS Technologies Tel: (505)-875-0600
| Function | Description |
|---|---|
| 16 interrupt generating digital inputs, 16 digital outputs, optically isolated 24V with interrupts, debounce, extended temperature range, and rear I/O. Model No. PMC-DIO-ETB | |
| 16 interrupt generating digital inputs, 16 digital outputs, optically isolated 24V with interrupts, debounce, extended temperature range, and front panel I/O. Model No. PMC-DIO-ETF | |
Switches | 32 opto-isolated high side switches with 24V, 0.5A capacity, watchdog timer, extended temperature range, and rear I/O. Model No. PMC-DRV32-ETB |
Switches | 32 opto-isolated high side switches with 24V, 0.5A capacity, watchdog timer, extended temperature range, and front panel I/O. Model No. PMC-DRV32-ETF |
| 64 TTL level I/O lines in eight-bit ports with ESD protection, interrupts, extended temperature range, and both front panel and rear I/O. Model No. PMC-TTL64-ET |
Technobox Tel: (609) 267-8988
| Function | Description |
|---|---|
Reconfigurable 155 Mb/s Fiber Optic | FPGA-based reconfigurable platform for implementing fiber optic interfaces that are not supported by standard chipsets. Altera Flex 10K70 standard; other population options may be available. Separate transmit/receive channels. Front-panel I/O (ST type). PCI interface implemented in PLX 9080. Part No. 2687 |
Reconfigurable Digital I/O | FPGA-based 80-channel reconfigurable digital I/O provides vehicle for implementing complex user-specific digital designs requiring high speed single-ended operation. 64 of 80 signals are available out the rear I/O, while all 80 signals are wired to front panel connector. Built around an Altera EPF10K100EQC240-2 FPGA. PCI interface implemented in PLX 9080. Part No. 2979 |
Digital I/O | 32-channels, individually programmed as set/reset or parallel read/write. Rear I/O interface only. Front panel LEDs (32) show nominal signal levels. Change in line states recorded in FIFO along with timestamp counter (30 ns resolution on each channel). FIFO capacity is 512 timestamp words. Part No. 2195 |
Digital I/O Subsystem | Single-wide PMC can accept up to 192 I/O lines from as many as 8 distributed I/O modules (P/N 2211) via a multi-drop twisted-pair ribbon cable. Each 82C55-based module supports 24 digital I/O lines. I/O direction is software controlled (default for all lines is INPUT). Front panel 50-pin SCSI-style connector. Part No. 2216 |
FPGA-based Digital I/O | Reconfigurable platform for implementing complex, user-specific digital designs. Altera Flex 10K70RC240-4 FPGA (standard). 96 channels - 32 front panel, 64 rear (groups of eight, each buffered by a 74FCT16245 buffer). R/C termination. 128Kx16b SRAM. FPGA configuration can be loaded from EPC1 EPROM or host. PLX 9050 PCI bus interface. PLL, 100 ns delay lines. Special receivers for controlling application timing. Part No. 2372 |
Reconfigurable RS422/RS485 Digital I/O | Reconfigurable platform for implementing complex, user-specific digital designs. Altera Flex 10K70RC240-4 FPGA (standard). 32-channels (RS422/485) available at both front (68-pin SCSI-type) and PN4 connectors. 128Kx32b SRAM. FPGA configuration can be loaded from EPC1 EPROM or host. PLX 9080 PCI bus interface. PLL provided for controlling application timing. Part No. 2674 |
Reconfigurable RS422/RS485 Digital I/O | Reconfigurable platform for implementing complex, user-specific digital designs. Altera CycloneEP1C12F324C8 (approx. 12K LEs). 32-channels (RS422/485) available at both front (68-pin SCSI-type) and PN4 connectors. 256Kx32b SRAM. FPGA configuration can be loaded from EP1CS4 EPROM or host. PLX 9656 PCI bus interface. ICS 1522 PLL provided for controlling application timing (Cyclone also has internal PLLs). Recommended for new application designs. Part No. 4289 |
RS422/RS485 Digital I/O | Multifunction Digital I/O board. Sixteen Z8536 based Digital I/O with Open Drain MOSFET drivers. Two 16550 Based UARTS with RS422/RS485 electrical.50-pin front panel connector; Rear PN4 I/O. Part No. 2628 |
TEK Microsystems Tel: (978) 244-9200
| Function | Description |
|---|---|
Data Port Interface | ANSI/VITA 17 Front Panel Data Port (FPDP) interface, software programmable selection of FPDP/TM, /R, or /RM. TTL and PECL STROBE support, 32-bit PMC bus @33MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-FPDP |
EIA-485 or TTL I/O | Customizable EIA-485 or TTL I/O, implements up to 32 EIA-485 I/O signals or 64 TTL I/O signals. 32-bit PMC bus @33 MHz,132 MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-DFLEX64 |
Parallel Data | Flexible, high performance parallel EIA-485 data transfer. Two independent 16-bit parallel interfaces, each of which can be configured for input or output under software control. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, variable word width, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-PDIO32 |
Input (EIA-644) | Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has two DS90CR286 28-bit interfaces and supports burst data rates up to 1.848 Gbps per 28-bit channel. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVI-2x28 |
Input (EIA-644) | Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has three DS90CR484 48-bit (36 bits utilized) interfaces for burst data rates up to 4.032 Gbps. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVI-3x36 |
Output (EIA-644) | Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has two DS90CR285 28-bit interfaces and supports burst data rates up to 1.848 Gbps per 28-bit channel. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVO-2x28 |
Output (EIA-644) | Uses the National Semiconductor Channel Link family of LVDS receivers to implement an EIA-644 interface between two systems over simple twisted-pair cabling. Has three DS90CR484 48-bit (36 bits utilized) interfaces for burst data rates up to 4.032 Gbps. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-LVO-3x36 |
ECL/PECL Input | Flexible, high performance parallel ECL/PECL input solution. 32-bit PMC bus @33MHz, 132MB/s data transfer, customizable FPGA, variable word width, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-PEI32 |
ECL/PECL Output | Flexible, high performance parallel ECL/PECL output solution. 32-bit PMC bus @33MHz, 132MB/s data transfer, customizable FPGA, variable word width, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-PEO32 |
Dual Fiber Optic I/O Module | 0-26.6 MB/sec. uses Cypress HOTLink encoder/decoders, supports two separate 400 Mbps input streams and two separate 400 Mbps output streams. 32-bit PMC bus @33 MHz, 132MB/s data transfer, customizable FPGA, 1MB FIFO memory for efficient DMA burst performance. Model No. FPMC-2HL400 |
Fiber Optic I/O Module | 0-26.6MB/sec. Uses Cypress HOTLink encoder/decoder, up to 266 Mbps using SC fiber connectors and 330 Mbps using copper media. 32-bit PMC bus @ 33MHz, 132MB/sec data transfer, 4KB FIFO for efficient DMA burst performance. Model No. FPMC-HL266 |
2-Channel Fiber Optic I/O Module | 60-400 Mbps. Uses Cypress HOTLink encoder/decoder, up to 400 Mbps using copper or fiber media. 32-bit @ 33 MHz PCI standard, 132 MB/sec data transfer. 64-bit 33 MHz PCI special order. 1 MB FIFO for efficient DMA burst performance. VxWorks drivers. Model No. FPMC-2HL400 |
2-Channel Fiber Optic I/O Module | 200 Mbps - 1.25 Gbps. Uses Cypress HOTLink encoder/decoder, with copper or fiber media. 64-bit PMC bus @ 66 MHz, 267 MB/s sustained data transfer, dual-port synchronous SRAM buffering. VxWorks drivers. Model No. FPMC-2HL1500 |
TEWS Technologies Tel: +49 4101 4058-0, (775) 686 6077
| Function | Description |
|---|---|
24V DC | 32 digital inputs, 24V DC, optically isolated; Fully programmable interrupt capabilities; Electron. Debounce; -40°C to +85°C. 50 pin SCSI-2 type connector in front panel (TPMC600-10), P14 I/O (TPMC600-20) |
24V DC | 16 digital inputs, 24V DC, optically isolated; Fully programmable interrupt capabilities; Electron. Debounce; -40°C to +85°C. 50 pin SCSI-2 type connector in front panel (TPMC600-11), P14 I/O (TPMC600-21) |
64 TTL I/O | User configurable FPGA with 300,000 system gates (Xilinx XCS300E-6); FPGA development tool: Free Xilinx ISE WebPack; 64 TTL I/O lines (programmable as in, out or tristate I/O with pull-up resistors in sockets); several clock options; ESD and overvoltage protection for each I/O line; -40°C to +85°C (TPMC630-10) |
32 Diff I/O | Same as TPMC630-10, but 32 Diff. I/O lines using EIA-422/EIA-485 programmable as in, out or tristate I/O with pull-up resistors in sockets. (TPMC630-11) |
32 TTL I/O 16 Diff. I/O | Same as TPMC630-10, but Programming of FPGA via IP Bus; 32 TTL and 16 Diff. I/O lines programmable as in, out or tristate I/O with pull-up resistors in sockets. (TPMC630-12) |
24V DC | 16 digital inputs, 24V DC, optically isolated, fully programmable interrupt capabilities, electron. Debounce; 16 digital outputs, 24V DC 0.5 A, optically isolated; High side switch; Overload and short circuit protection; -25°C to +85°C. 50 pin SCSI-2 type connector in front panel (TPMC670-10), P14 I/O TPMC670-20) |
24V DC | 8 digital inputs, 24V DC, optically isolated, fully programmable interrupt capabilities, electron. Debounce; 8 digital outputs, 24V DC 0.5 A, optically isolated; High side switch; Overload and short circuit protection; -25°C to +85°C. 50 pin SCSI-2 type connector in front panel (TPMC670-11), P14 I/O (TPMC670-21) |
24V DC | 16 digital inputs, 24V, optically isolated, fully programmable interrupt capabilities, electron. debounce, 24V DC 0.5A, optically isolated; Overload and short circuit protection; HD68 SCSI-3 type connector in front panel; -25°C to +85°C. 16 digital high side switch outputs (TPMC671-10), 16 digital low side switch outputs (TPMC671-11) |
24V DC | 16 digital inputs, 24V, optically isolated, fully programmable interrupt capabilities, electron. debounce, 24V DC 0.5A, optically isolated; Overload and short circuit protection; P14 I/O; -25°C to +85°C. 16 digital high side switch outputs (TPMC671-20), 16 digital low side switch outputs (TPMC671-21) |
Inputs/Outputs (5V TTL) | 64-bit TTL I/O; 8 x 8-bit ports; HD68 connector in front panel, 7 of these 8-bit ports available at P14; basic operating modes: byte I/O, 2x16-bit port with handshake, 1x 32 bit port with handshake; Interrupt capability; -40°C to +85°C (TPMC680-10) |
24V DC | 32 digital outputs, 24V DC 0.5 A, optically isolated; High side; Overload and short circuit protection; -25°C to +85°C. 50 pin SCSI-2 type connector in front panel (TPMC700-10), P14 I/O (TPMC700-20) |
24V DC | 16 digital outputs, 24V DC 0.5 A, optically isolated; High side; Overload and short circuit protection; -25°C to +85°C. 50 pin SCSI-2 type connector in front panel (TPMC700-11), P14 I/O (TPMC700-21) |
| 32 single-ended/16 differential channels of 16 bit multiplexed analog input, 8 channels of 16 bit analog output, 16 digital I/O lines and a 32 bit multi-purpose counter; -40°C to +85°C (TPMC851-10) |
Thales Computers Tel: +33 (0)4 98 16 34 00 - (732) 494 1010
| Function | Description |
|---|---|
Parallel I/O | 64 channels of 3.3 volt (5 volt compatible) parallel I/O. Independently programmed input/output direction via PCIbus registers. All I/O signals have input protection circuitry and pull-up resistors to 3.3 volts. Model No. PMC-PIO |
| 64 Channel, 3.3V (5V compatible) parallel I/O; independently programmable as input or output; conduction or convection cooled (P/N I-/R-/M-PMC Carrier) |
VMETRO Tel: (281) 584-0728, +47 22 10 60 90
| Function | Description |
|---|---|
with FIFO | FPDP/FPDP II compatible, 400MB/sec FIFOs up to 128K words. Linked-list DMA. Options: Async or user-conf I/O. TTL, LVDS, ECL I/O, Model No. DPIO2 |