1000 Mbytes/s Range Possible
Tel.: 07231 9734-20
FAX. 07231 9734-87
e-mail: a.lenkisch@.trenew.de
Internet: http://www.trenew.com
Recent developments within the VMEbus community has seen the bus speed doubled three times in a very short period of time. Due to the asynchronous protocol, this increase in performance has been achieved with full compatibility to all earlier boards.
The original theoretical data rate introduced 16 years ago was 40 Mbytes/s with the Block Transfer (BLT) Protocol. For a long time this was sufficient. But with much faster processors, the original data rate becomes more and more a bottleneck. By multiplexing data and address lines and including LWORD, the bus speed (or data rate) was doubled for the first time to 80 Mbytes/s theoretical speed. This was proposed in 1989 and approved in 1994 with ANSI/VITA-1 [1] as the Multiplex Block Transfer Protocol (MBLT).
Currently, the VME64 Extensions Standard [2] is under balloting by ANSI. Reducing the two-fold handshake to a single and using both the rising and falling edges of the handshake signals (strobe and acknowledge). This approach is known as the 2e(dge)VME protocol. Also, by using the new ETL [3] incident wave switching drivers, the time window has been halved to 50 ns and the speed doubled a second time to 160 Mbytes/s.
The third doubling to 320 Mbytes/s was introduced by Bustronics / Arizona Digital, using a patented "star wiring" backplane technology to achieve incident wave switching by an alternative method. This very short time window of 25 ns for a data transaction relates with a transfer rate of 320 Mbytes/s can only realised with a source synchronous protocol.
This new performance using the 2edge Source Synchronous Protocol (2eSST) [4] was presented during last year. It is achieved by omitting the remaining acknowledge signal after each data beat and placing them at the end of a block transfer. This saves all the waiting times, needed for the return of this handshake signal. The settling time for a stable digital signal is also omitted by using incident wave switching. In the case of the "VME320 Technology" as a synonym for a star wired backplane, incident wave switching is realised by using very slow edge rates where the reflections merge instead of using stronger drivers. By removing the need for reflections all of the signals, data and strobe, run in one direction over the backplane, "synchronous to source".
Using older protocols, the data speed is limited by the propagation time through the backplane. The next data beat may start only, when the successful reading of the preceding data is acknowledged by the receiver. This requires a signal propagating opposite with the direction of the data stream.
A further limitation of speed is originated by the reflection, independent of whether incident wave switching is achieved or not. With increasing data speed or physical frequency,
Fig. 1
Bus speed is limited by "resonant limitation"
with increase of speed of the source signal (A), on high impedance traces due to high propagation delay, the reflected wave superimposes with the following edge (B) of the source signal and results in noise (C). Low impedance traces will result in shorter propagation time and can improve performance (D).
the next edge of the signal arrives at the same time as the reflection and both superimpose on each other. But both have different slope directions: if the reflection comes from a rising edge, the reflection is also rising, but the following signal edge is a falling one. Such superimposed signal is no longer readable as a clear digital signal, it appears like noise voltages centred near the threshold region with small spikes which occur at the time when the edges merge. This kind of limitation may be called resonant limitation. See Fig. 1.
So we have two kinds of limitation of speed:
A further increase of bus speed can be achieved by using lower impedance traces to achieve shorter propagation delays [5]. But to get a much higher increase of speed, we need a new quality. This new quality is the source synchronous protocol. Now the limitation of speed will only be caused by the skew of all the signals because there is no longer the need for signals to run backward towards the source. The reflections must arrive after a very short time, much earlier than the next signal edge occurs, as indicated or must be removed. The combination of low impedance backplane with much faster running signals and a source synchronous protocol will open the way into the future.
Fig. 2
2 edge Source Synchronous Protocol with timing parameters;
depending of write or read cycle, strobe may be DSn* or DTACK*
The data may be read at the destination, when the latest data signal has reached one set-up time before the fastest strobe has arrived and, vice versa, the fastest data must be still valid one hold time longer after reaching the slowest strobe [4,6], see Fig. 2. The absolute running time, without skew, is identical for all the signals and may be subtracted because all the signals run in the same direction. So the difference between the fastest and slowest signal, the skew, becomes the bottleneck of performance. It is therefore recommended to use a low skew backplane and transceiver technology. As shown in table 2, the backplane and transition skew of the star wiring backplane contribute greatly to the overall skew. This is due to the very slow edges of this technique. Using low impedance backplanes and the stronger ETL incident wave switching drivers will reduce the skew considerably as shown in the following paragraph.
The total skew of the transmission path is determined by the skew of the source, the skew of the transmission line in the backplane and the skew of the destination (Fig. 2).
The source skew of the ETL [3] driver is taken from the ABTE TI-Data Book [7] as the difference between fastest and slowest gate delay from port "B" to port "A":
tpd max - tpd min = 5,2 ns - 1,5 ns = 3,7 ns.
This is the worst case skew over the whole voltage and temperature range. The maximum skew between any signals on a single board will be greatly reduced due to the reduction in temperature and supply voltage variation.
An alternative to a star wired backplane, acting as a lumped element of inductance and capacitance, making very smooth signal edges, a backplane using transmission line signals is proposed with this paper. Due to the slow signal edges, generated by the "centred capacitance" of the star wired backplane, higher frequencies over this backplane seems to be limited [8]. This is the reason for using low impedance backplanes traces [5] or, the reflections must be removed. The influence of these signal reflections will be investigated in a future paper.
The backplane skew is calculated by the difference in propagation delay, caused by load capacitance tolerances:
|
Loads |
cap. Value |
tolerance |
|
BP-Via |
0,8 pF |
5% |
|
Connector |
0,8 pF |
5% |
|
Board-Via |
0,6 pF |
5% |
|
Trace |
4,5 pF |
15% |
|
Package |
1,0 pF |
10% |
|
Transceiver |
8,0 pF |
25% |
|
Capacitance per slot |
15,7 pF |
|
|
weighted tolerance |
18,3 % |
Table 1
The trace capacitance is calculated by assuming a 60 W trace of a length of 1,5 inches.
Calculating the difference of propagation delay, the following basic formula is applied:
(1)
Where tpd is the propagation delay of the loaded trace, tpdo is the propagation delay of an infinite trace in an homogenous dielectric (180 ps/in.) and Co is the intrinsic capacitance of a trace, assumed to 3,9 pF/in. for a trace of 46 W . The backplane skew is calculated as 0,4 ns and will reduce with lower impedances. The backplane skew of a transmission line backplane is slightly lower than of a star wiring backplane. This calculation assumes a fully loaded backplane. With empty slots the backplane skew compared to loaded backplanes increases and lower data rates are achieved. To obtain the highest data rate, all slots shall be populated, for example with dummy loads of low tolerances of the capacitive load.
The destination skew is caused by variations in the receiver threshold and may be estimated by the time which is needed for the signal to cross the region between the "LOW" and "HIGH" level. Using the fast and strong ETL drivers will increase the performance compared with the star wiring backplane. Instead of 6 ns skew [6] we will get a value of 0,4 ns: The slope is assumed to approx. 0,5 V/ns and the levels are well known with 1,4V for "LOW" and 1,6V for "HIGH".
The overall cycle time may be calculated by adding all the skews, the setup and hold times [4] (Fig. 2):
Using the same calculation scheme and the same assumptions as it was made for the star wiring backplane [6], we may calculate as follows:
|
skew description |
VME533 |
Trenew |
|
Tdata-skew |
5,0 ns |
3,7 ns |
|
+ Tbackplane-skew |
1,5 ns |
0,4 ns |
|
+ Ttransition-skew |
6,0 ns |
0,4 ns |
|
+ Tdata-setup |
1,5 ns |
1,5 ns |
|
+ Tstrobe-skew |
1,0 ns |
1,0 ns |
|
+ Tdata-hold |
1,0 ns |
1,0 ns |
|
Tcycle |
16,0 ns |
8,0 ns |
|
data rate |
500 MB/s |
1000 MB/s |
|
data frequency |
31,3 MHz |
62,5 MHz |
- Table 2
VME533 is the calculation for the star wiring technique of Drew Bearding [6].
Theoretically the strobe skew should be the same as the data skew, but in practise, a reduction may possible. The strobe is only one signal instead of 64 signals and uses the same driver, backplane trace and receiver, all at nearly the same temperature and supply voltage. That's why the strobe skew is assumed to 1 ns [6].
The data rate is defined as the number of data bytes driven per second along the data transmission path:
data rate = 1(second) *8 Bytes / cycle time. The physical data frequency can be calculated by dividing the data rate by 2*8 Bytes. The factor "2" arises from the fact that at the Period T of a square wave signal two data beats will occur.
This estimation shall indicate that the increase of data rate or the increase in performance of the "old" VMEbus is not yet achieved. This paper shall only give an approximate estimation of a data rate which may possible by using stronger ETL drivers and a backplane comprising the well known transmission lines, but with a change in impedance or with removal of reflections. The calculations are made with the same assumption as used in the paper of Drew Bearding [6] without any detailed check as to the degree of their accuracy.
In a future paper a deeper discussion of the skew times and compatibility aspects shall be performed as well as presented measurements.
References
VMEbus International Trade Association, 7825 East Gelding Drive,
suite 104, Scottsdale, Arizona 85260
Internet: http://www.vita.com
Enhanced Tranceiver Logic Specification
VMEbus International Trade Association, 7825 East Gelding Drive,
suite 104, Scottsdale, Arizona 85260
Internet: http://www.vita.com
Source Synchronous Transfer Draft Standard
VMEbus International Trade Association, 7825 East Gelding Drive,
suite 104, Scottsdale, Arizona 85260
Internet: http://www.vita.com