From: "Serge TISSOT" <st@cetia.fr>
Subject: P2CI task group 27 Status
To: <MThompson@Pentair-EP.com>
Cc: "John Rynearson" <techdir@vita.com>, <a.lenkisch@trenew.de>, <ulrich.wallenhorst@harting.com>, "Jérome Merlivat" <jme@cetia.fr>, "PHVINCENT" <phv@cetia.fr>, "Robert Negre" <rn@atch.cetia.fr>
Mike,
here is the status of the P"CI task group 27; could you please report
this status to the next November VSO meeting ?
We finally finished our testing of the P"CI bus with actual prototypes of
Cetia VME SBC, Schroff 6 slot P"CI backplane and Trenew 3 slot P"CI
backplane.
Everything was OK for the functionnality and worked in compliance with the
P"CI draft. However, to get an acceptable cross talk level between VME P2
signals and P"CI signals (below 200 mV), we were obliged to increase
the series resistor on P"CI signal from 10 Ohms to 47 OHms. Unfortunately,
this increased the propagation delay over the bus and now leads to a PCI
frequency limitation around 25 MHz for the 6 slot backplane.
We believe such a frequency limitation for safe P"CI operation is a serious
restriction for today's and to morrow's systems and would limit the
acceptance
of the P"CI bus as a general and open link between VME SBC cards.
Consequently, CETIA plans to stop its P"CI standardization efforts on the P2
connector. Interconnecting VME SBCs through a high speed 64 bit PCI passive
link is still very attractive and CETIA will use the results of P"CI
technology developped
so far to match this goal.
Thanks to M. Thompson, A. Lenkisch and U. Wallenhorst for their active
participation
in the task group effort.
Serge TISSOT
CETIA SA, a Thomson CSF Subsidiary
150, rue M. Berthelot / ZI Toulon Est / BP 244 / 83078 TOULON Cedex / France
Phone: (33) 4 94 16 34 00 Fax: (33) 4 94 16 34 01
Email: stissot@cetia.fr Web: http://www.cetia.com