*** Reading Skordou et al

*** Reading Skordou et al. (US 5,293,589) CLAIM 1 *** *** on VITA 1.4-199x Draft 0.4 ***

March 20, 1998

Introduction

This document reports my opinion as to the applicability of Skordou et al., US Patent No. 5,293,589 CLAIM 1 on the VITA 1.4-199x (draft 0.4) standard .

Methodology

It is important to note that patent documents are intended to be read against an "invention"(i.e. a product). This is very hard to do with a standards document, as these are not an "invention"in the purest sense of the word. To overcome this problem, the following methodology is used:

The complete standards document is read.

The complete patent document is read.

VMEbus board and/or system designs, which conform to the standard, are imagined in my "minds eye". The indicated claim(s) of the patent document are then read against the imagined design.

If the patent claim(s) appeared to read on the imagined designs, then the results of the investigation are reported to the VSO. If the patent claim(s) do not appear to read on the design, it is not reported.

Summary of Skordou et al. ("589) CLAIM 1:

"A computer comprising a plurality of disconnectable plug-in modules, including a first module, subsequent modules including a second module and preceding modules including a third module, at plug-in locations of the computer, a bus connecting the modules to one another, the bus including a daisy-chained acknowledging signal line for carrying an acknowledging signal between the modules,"

[This describes a backplane computer (VMEbus or otherwise) with at least three modules and a daisy-chain].

"...means associated with each of said modules for and operatively associated with a single one of said modules for relying said signal past its associated module if the signal is intended for said subsequent modules,"

[This describes the BACKPLANE daisy-chain logic].

"...a decoding circuit on each one of said modules for preventing a further relaying of the of the signal by the first module if the signal is intended for the first module,"

[This describes the daisy-chain logic LOCATED ON EACH BOARD].

"...the means for relaying and the decoding circuit of the first module processing the acknowledging signal within a predetermined response time, a holding circuit associated with a corresponding one of said modules at the plug-in location for said corresponding module,"

[This also describes the backplane daisy-chain logic. The term 'holding circuit' refers to logic which 'holds' the daisy-chain].

"...said holding circuit having an input connected said acknowledging signal line and activated in response to a disconnection of the corresponding module from its plug-in location; and means in the holding circuit for forwarding the acknowledging signal along the acknowledging signal line when a delay forming an individual lag time for the corresponding module,"

[This means that the backplane logic will be aware that its card has been removed, and pass the daisy-chain accordingly].

"...a sum of said individual lag times for said modules at all said plug- in locations being a total lag time, said total lag time being less than the predetermined response time."

[I was a little confused over this last statement. However, I think it was put here to differentiate their method over the mechanical connector methods (which certainly came out prior to this patent). The mechanical connectors work instantly, whereas by this method the backplane logic (no matter how fast it is) will always take some non- zero time].

- END OF CLAIM 1

Conclusion

Skordou et al. Claim 1 does appear to read on the live insertion standard. It doesn't use the live insertion pins, but it's broad enough to anticipate it.

Representatives of Force Computers GmbH, the assignee of the invention by Skordou et al., have indicated at earlier VSO meetings of their willingness to licence this patent for US $1.

Claim 1 may be also be overclaimed (i.e. it may be too broad). This claim is so broad as to encompass virtually all active backplane daisy chain devices. For example, Martin Blake (VERO) sent the results of some of their daisy-chain patent searches, which may include prior art:

>The last search I conducted for daisy chain circuitry was back in 1992, a >number of patents and patent applications were discovered: > >JP 63-150755 A Fujitsu 23 June 1988 >"Interface device" >Notes: Removal of a board from a slot causes first signal line to OR- gate >to be pulled down while second signal line to AND-gate is pulled up. > >JP 58-125124 A Mitsubishi Densi KK 26 July 1983 >"Parallel Bus controller" >Notes: Interposed bypass circuit on daisy chain comprises an inverter, two >AND-gates and an OR-gate > >JP 58-163033 A Tokyo Shibaura Denki KK 27 Sept 1983 >"Interruption controlling system of input and output device" >Notes: Interrupt bypass circuit on daisy-chain comprises an inverter, two >AND-gates and two pull-up resistors. > >JP 63-140360 Fujitsu Ltd 11 June 1988 >"Daisy chain device" >Notes: Interposed bypass circuit on daisy chain comprises comparator, >inverter two AND-gates and an OR-gate. Comparator goes HI when there is a >LO signal on the out terminal or when the board is absent. > >EP 0 265 574 A IBM Corp 4 May 1988 >"Daisy chain bus access configuration" >Notes: Logic circuits on daisy-chain to bypass unplugged or malfunctioning >boards/connectors without undue delay. Functioning boards signal 'Adapter >present' status. Boards may be grouped ond their signals OR-ed to pass >grant signal to succeeding groups or indicate that it is trapped. > >EP 0 271 626 A IBM Corp 22 June 1988 >"Bypass mechanism for daisy chain connected units" >Notes: Gating logic controls bypass line to prevent signals being trapped >by disconnected or malfunctioning boards in daisy chain. > >US 4 380 052 Burroughs Corp 12 April 1983 >"Single transmission bus data network employing a daisy-chained bus data >assignment control line which can bypass non-operating stations" >Notes: Board stations in closed loop daisy chain have means for determining >whether any station is inactive > >US 4 408 300 Burroughs Corp 4 Oct 1983 >"Single transmission bus data network employing an expandable daisy-chained >bus data assignment control line" >Notes: As previous but for boards with higher & lower priorities. > >US 4 774 625 Mitsubishi Denki KK 27 Sept 1988 >"Multiprocessor system with daisy-chained processor selection" > >JP 58-56119 A Fujitsu KK 2 April 1983 >"Detour system for signal" >Notes: Buffers are turned on by voltage Vcc to pass signals of preceeding >board when Ioc is removed. > >JP 59-132232 A Mitsubishi Denki KK 30 July 1998 >"Priority Circuit" >Notes: Interposed buffer on daisy chain is grounded when board is present >to transmit signal on input line but pulled high by resistor when slot is >vacant to transmit signal to next board > >JP 60-225962 A Mitsubishi Denki KK 11 Nov 1985 >"Priority Control Circuit" >Notes: Bypass circuit on daisy chain comprises an inverter, an NAND-gate, >and a microswitch closed by the presence of a board in a slot > >JP 60-14366 A Fuji Xerox KK 24 Jan 1985 >"Daisy Chain Circuit" >Notes: Normal operation of daisy chain when boards are removed is >maintained by use of plural AND-gates in onboard logic circuits. > >The following were also cited as prior art in applications: > >JP 60-84653 A >JP 62-251952 A >JP 63-6651 A >JP 1-26963 A >JP 1-76141 A > >The list contains both granted patents and applications. The reason I have >included them all is because there may be cases where the invention has >been published and abandoned, thus establishing "right to use". We may be >able to use this to ensure proper defense for any proposed solution. I have >copies or abstracts of most of these (but can't read Japanese!). The >information will have changed since this search was conducted (some >applications presumably will have been granted) and new applications sought >(Force / Systolic etc.). > >Martin >

Repectfully submitted by,

Wade D. Peterson Consultant to Industry Minneapolis, MN USA

*** Reading Husak et al. (US 5,317,697) CLAIM 1 *** *** on VITA 1.4-199x Draft 0.4 ***

March 20, 1998

Introduction

This document reports my opinion as to the applicability of Husak et al., US Patent No. 5,317,697 CLAIM 1 to the VITA 1.4-199x (draft 0.4) standard .

Methodology

The complete standards document is read.

The complete patent document is read.

VMEbus board and/or system designs, which conform to the standard, are imagined in my "minds eye". The indicated claim(s) of the patent document are then read against the imagined design.

Summary of Husak et al. ("697) CLAIM 1:

"Apparatus to permit insertion of an electronic sub-assembly into a live electronic assembly comprising: a first connector portion in continuous electrical communication with said live electronic assembly,"

[This describes a backplane connector (VMEbus or otherwise)].

"...a second connector portion in continuous electrical communication with said sub-assembly and adapted for mating with said first connector portion;"

[This describes a PC board connector (VMEbus or otherwise)].

"...at least one pin of a first length, at least one pin of a second length, and at least one pin of a third length each being disposed on one of said first and second connector portions; at least one first contact, at least one second contact, and at least one third contact each being disposed on the other of said first and second connector portions such that said contacts oppose respective first, second and third length pins for mating therewith upon mating of said first and second connector portions;"

[This describes, among other things, the 160-pin VME64 connectors. The three pin lengths correspond to the precharge (first pin), main +5 VDC power pins (second pin) and live insertion logic (third pin).

I measured the lengths on a 160 pin Harting plug connector as follows:

Relative pin length, voltage precharge (1st contact): 0.005" Relative pin length, +5 VDC power pins (2nd contact): 0.060" Relative pin length, live insertion pins (3rd contact): 0.085"

Therefore, the three pin lengths on the Harting 160 pin connector match the claim specification.

It should also be noted that if the board uses all +3.3 VDC power rails, then a board can be designed so that the claim specification is not met].

"...a controlled active current limiting device;"

[This describes the circuit required by Rule 3.2 of the VITA 1.4 Draft 0.4 standard].

"...a first power source operative to apply a bias voltage to said sub- assembly upon engagement of said at least one pin of said first length and said at least one first contact;"

[This describes the voltage pre-charge pins at the edges of the 160-pin VME64 connector(s)].

"...a controller for controlling current passing through said controlled active current limiting device and operative to apply power to said sub- assembly at a controlled rate in response to engagement of said at least one pin of said at least one pin of said second length and said at least one second contact,"

[This describes the power applied to the board through the main +5 VDC pins located on the center three rows of 160-pin VME64 connector. Furthermore, this current surge is limited by the Rule 3.2 ramp-up circuit.

One interpretation of this section of the claim could be that the power switches on the front panel would prevent power-up on the board. Another interpretation of this claim would be that the power switches themselves constitute powered devices].

"...a bypass path for bypassing said controlled active current limiting device effected by engagement of said at least one pin of said third length and said at least one third contact; and"

[One interpretation is that this describes the live insertion signal pins located on the outer row of the 160 pin VME64 connector.

Another interpretation states that this is a bypass route around the turn- on power circuit (which could be used to lower the "head-room" required by semiconductors].

"...bypass circuitry operative to sense engagement of said at least one pin of said third length and said at least one third contact and to determine a status of engagement thereof and to route transmissions to said subassembly and in the alternative to route transmissions away from said subassembly in accordance with said status."

[This describes the live insertion logic circuit, and includes (a) live insertion status signals to the rest of the system and (b) status to the daisy-chain control logic on the backplane].

- END OF CLAIM 1

Conclusion

It is apparent that VMEbus boards designed to the standard could interfere with Husak et al. Claim 1. However, it is felt that boards could be easily designed around this claim, and still conform to the standard.

*** RECOMMENDATIONS FOR THE VSO ************************

After searching for, and reading numerous patents against the VME64x Live Insertion Draft Standard (VITA 1.4-199x, Draft 0.4), I recommend the following two action items:

Investigate the French patent by Philippe Sevigne (i.e. the Systolic patent) further. This will require either of the following activities:

(a) Find a French speaking person who is skilled in the art of VMEbus technology, and is capable of reading the patent document. This person will review the patent, and report back to the VSO.

- or -

(b)

Obtain an English language translation of the patent document from a skilled patent interpreter. This will then be reviewed by the VSO.

Add the following OBSERVATION to the VITA 1.4 standard:

OBSERVATION 2.1

There are virtually unlimited ways to design products that conform to this standard. Users of this document are cautioned that some implementations of this standard may infringe on the patent rights of others (in some countries). Before manufacturing, importing, advertising or selling a product based on this standard, it is recommended that the user review the product against the following patents:

Husak et al. METHOD AND APPARATUS FOR LIVE INSERTION AND REMOVAL OF ELECTRONIC SUB- ASSEMBLIES. US Patent No. 5,317,697

Sevigne, Philippe. DISPOSITIF ELECTRONIQUE PERMETTANT LA CONNEXION ET LA DECONNEXION D'UNELLGNE DE BUS D'UN SYSTEME INFORMATIQUE. Republique Francaise No. de publication: 2,671,887, No d'enregistrement national: 91 00778

Skordou et al. CIRCUIT WITH PREDETERMINED DELAY FOR SELECTIVELY RELAYING INTERRUPT SIGNALS THROUGH A DAISY-CHAIN OF LINKED MODULES UPON REMOVAL OF A MODULE FROM A SLOT. US Patent No. 5,293,589

Respectfully submitted by,

Wade D. Peterson Consultant to Industry