By John Rynearson, Technical Director, VITA
One of the advantages of using a VMEbus system is adaptability and flexibility. Many times the requirements for a project change and with a modular approach like VMEbus changes can be easily accommodated. What happens if performance requirements increase and you run out of bandwidth on the VMEbus? One solution is to use a secondary subsystem bus. Rows A and C on the VMEbus P2 connector are labeled as "user-defined" and are can be used for one of two purposes: to bring I/O to the board or for a secondary subsystem bus.
In the early days of VMEbus when a single CPU board only held 128K of DRAM secondary buses were used primarily as memory extension buses. The VMXbus, an early secondary subsystem bus, supported 24 bits of addressing and 32 bits of data. Limited capabilities for interrupts and arbitration were also supported. The VMXbus found its greatest use as a memory extension bus. Certain applications required more memory than could fit on a VMEbus CPU module. The idea of using VMXbus was to take all these board to board memory accesses off of the VMEbus. Because the VMXbus was limited to 24 bit addressing, a modification to the VMXbus was developed by Motorola called the MVMX32 bus. The MVMX32 bus was never formally standardized, however. The MVMX32 bus contained 8 more address lines for full 32 bit addressing and a cacheable read cycle was added. Both VMX and MVMX32 only supported a six slot backplane. The existence of two very similar secondary buses caused confusion in the marketplace. To solve this problem, the best features of VMX and the MVMX32 were combined.
VSB (VME Subsystem Bus) was the successor to the VMXbus and the MVMX32bus. It contains features similar to both and added the ability to handle STATUS/ID information during interrupt acknowledges cycles. It also supports a six slot backplane. Over the years VSB has become the secondary bus of choice for many VMEbus applications. Various VMEbus manufacturers offer products with VSB interfaces and VSB is also a popular mezzanine add-on option.
Besides being useful as an extended memory bus, a secondary bus can be used to reduce overall bus traffic on the VMEbus. For example, data and event traffic on the VMEbus for a specific real-time application may included the following: data coming in from a high speed link, data coming in from several analog to digital converters, data transfers between several CPU modules, data transfers out to a network link, and data transfers to a high performance disk interface. If all of the real-time requirements cannot be met with VMEbus bandwidth, then it makes sense to off-load some of the data traffic to another bus. In the above example, the continuous data transfers between the disk and the CPU board could be put onto VSB freeing up the VMEbus.
VSB uses the A and C rows on the P2 connector to provide for 64 bused signals. A standard VMEbus J2 backplane does not bus rows A and C. To support VSB you need either a "piggy-back" VSB printed circuit backplane, which can be plugged onto the standard VMEbus J2 backplane or a special J2 VSB backplane that has the A and C rows already bused. Either approach is acceptable. VSB was approved as an IEEE standard in 1988.
In the past, VSB was the most common secondary bus. However, with the need for higher data transfer rates other technologies are coming to the P2 bus. Raceway is a high performance circuit switched crossbar architecture that is currently undergoing ANSI canvass balloting process. A single connection provides 160 Mbytes/sec peak and 150 Mbytes/sec sustained data rates. Additional connections can provide additional bandwidth.
Another P2 bus undergoing the ANSI canvass ballot process is SCSA (Signal Computing System Architecture). SCSA is oriented to telephony applications such as call processing and focuses not on raw data transfer speed, but on the functional requirements of telephonic voice and facsimile media streams.
Another high performance P2 bus currently undergoing standardization within the VITA Standards Organization (VSO) is SkyChannel from Sky Computers. SkyChannel is a packet switched architecture that can provide rates up to 160 Mbytes/sec or 320 Mbytes/sec depending on configuration.
The decision by the VMEbus standard developers to supply 64 user defined I/O lines was farsighted. It provided the means for the implementation of secondary subsystem buses to enhance VMEbus performance. Now new secondary subsystem buses are being developed that will allow the use of VMEbus in a widening range of applications.
This page last updated: Sep 19, 1999
Reprinted from the VITA Journal with permission from VITA.