This is a complete listing of the VITA standards, along with their current status.
|ANSI/VITA 1.0-1994 (S2011)||
VMEbus or VME64
|The VME64 standard establishes a framework for 8-, 16-, 32, and 64-bit parallel-bus computer architectures that can implement single and multiprocessor systems. This bus includes the four basic sub-buses: (1) data transfer bus, (2) priority interrupt bus, (3) arbitration bus, and (4) utility bus. The data transfer bus supports 8-, 16-, 32-, and 64-bit data transfers in multiplexed and non-multiplexed form. The transfer protocols are asynchronous with varying degrees of handshaking dependent on the speeds required. The priority interrupt subsystem provides real-time interrupt services to the system. The allocation of bus mastership is performed by the arbitration subsystem which allows the implementation of several prioritization algorithms. The utility bus provides the system with power plus power-up and power-down synchronization. The mechanical specifications of boards, backplanes, subracks, and enclosures are based on IEC 297 and IEEE 1101.1 specifications, also known as the Eurocard form factor. Additional standards exist that can be used as sub-busses to this architecture for data transfer transactions, peripheral interfaces and intra-crate communications among compatible modules.||ANSI Stabilized|
|ANSI/VITA 1.1-1997 (S2011)||VME64x Extensions||VME64x is an extension of the ANSI/VITA 1-1994, VME64 standard. It defines a set of features that can be added to VME32 and VME64 boards, backplanes and subracks. These features include a 160 pin connector, a P0 connector, geographical addressing, voltages pins for 3.3V, a test and maintenance bus, and EMI, ESD, and front panel keying per IEEE 1101.10.||ANSI Stabilized|
|ANSI/VITA 1.3-1997 (S2011)||VME64x 9U x 400 mm Format||This standard defines a 9U x 400 mm board layout for use within the VMEbus framework.
|ANSI/VITA 1.5-2003 (S2014)||VME 2eSST||An extension of the ANSI/VITA 1-1994, VME64 and ANSI/VITA1.1-1997, VME64x standards. It defines a transfer protocol, based upon source synchronous concepts that permit the VMEbus signalling to operate at rates to at least 320MB/s. The 2eSST protocol requires low skew between signals and monotonic rising and falling edges on the signals. To meet these requirements, limited length backplanes, special backplane topologies and/or enhanced transceivers are required. The standard calls for enhanced bus transceivers with controlled rise and fall times, tightly defined thresholds, low part-to-part skew and LVTTL levels.||ANSI Stabilized|
|ANSI/VITA 1.6-2000 (S2011)||Keying for Conduction-cooled VME64x||An extension of the ANSI/VITA 1.1-1997, VME64x standard. It defines an alternate keying system that can be added to VME64x boards and backplanes in a conduction cooled environment (IEEE 1101.2) where keying as defined in the VME64 Extensions standard cannot be applied.||ANSI Stabilized|
|ANSI/VITA 1.7-2003 (S2014)||Increased Connector Current Level||The P1/J1 and P2/J2 current rating limits of the 3 row DIN and 5 row DIN connector pins listed in the DIN41612, IEC 603-2 and 61076-4-113 standards are based on full loading of the connector. In VME, VME64, and VME64 Extensions applications, the power pins represent only a small fraction of the total number of pins and are spread throughout the connector. The remaining pins are used to carry electrical signals, which add a negligible heating contribution. The net effect is that the connector heating is less, which allows a higher current carrying capacity.
Power contacts of connectors tested and certified in accordance with this standard are capable of passing 2.0 amps per contact on a selected group of pins. The standard has been verified by testing connectors from multiple vendors and it has been developed and approved by a broad cross-section of the VMEbus community.
|ANSI/VITA 3-1995 (S2011)||Board Level Live Insertion||This standard identifies methodologies through which a faulty board can be removed from a system and a replacement board can be inserted while the system continues to operate. The primary motivation for supporting Board Level Live Insertion within the VMEbus environment is to enhance the current VMEbus standard while maximizing the use of existing off-the-shelf VMEbus products.||ANSI Stabilized|
|ANSI/VITA 4-1995 (S2011)||IP Modules||This standard defines a versatile module, known as an "IP module." These modules provide a convenient method of implementing a wide range of I/O, control, interface, slave processor, analog and digital functions. IP modules, about the size of a traditional business card, mount parallel with a host Carrier board, which provides host processor or primary bus interfacing, as well as mechanical means for connecting the IP module's I/O to the outside world. Typical Carriers include standalone processors, DSP based carriers, as well as desktop buses and VME based boards. This specification includes mechanical, host bus electrical, and logical definition of I/O space, memory space, identification space, interrupts, DMA, and reset functions. Two physical sizes, two fixed clock rates, and multiple data width sizes to 32-bits are defined.||ANSI Stabilized|
|ANSI/VITA 4.1-1996 (S2011)||IP I/O Mapping to VME64x||With the development of the VME64x, 205 user defined I/O pin are available for rear backplane I/O. It is practical to route multiple IP's I/O through the VME64x backplanes. This standard defines the mapping of the 50 user defined I/O pins from the IP module (ANSI/VITA 4-1995 (R2002)) I/O connectors to VME64x board's rear I/O connectors in a consistent method across all VME64x boards, backplanes and rear I/O transition boards.||ANSI Stabilized|
|ANSI/VITA 5.1-1999 (S2011)||RACEway Interlink on VME||This standard provides a definition of the data link protocol and physical interface of a high performance extension to the VMEbus standard. This extension consists of high bandwidth, low latency interconnects across a VMEbus computer chassis backplane using the P2 connector. Bi-directional connectivity between boards in a VMEbus chassis is achieved through the use of a network of crossbar switches with point-to-point interconnects. RACEway Interlink is a VMEbus enhancement that can deliver up to 3.2 Gbytes/sec of scalable bandwidth over rows A, C, D and Z of the P2 connector in a standard VMEbus chassis. In addition to increased bandwidth, RACEway Interlink offers: 1) low latency, deterministic transactions, 2) concurrent point-to-point transactions for multiple simultaneous transfers, and 3) scalable bandwidth so total bandwidth increases as more slots are added. Many new applications, especially those with multiple processors and multiple real-time I/O interconnects, require these capabilities.||ANSI Stabilized|
|ANSI/VITA 6-1994 (S2011)||Signal Computing System Architecture (SCSA) on VME||The Signal Computing System Architecture (SCSA) standard establishes a framework for the inter- and intra-system transfer of serial media data and control information oriented toward the development of high density call and voice processing products and systems. The SCSA architecture is application specific and is embodied as a family of buses that are defined in this physical layer of the specification to reside on the VMEbus J2/P2 connector. The SCSA buses coexist with products compliant with ANSI/VITA 1-1994, VME64. SCSA at the physical level consists of two separate subbuses, a sixteen line TDM data transfer bus called the SCbus, and a serial, peer-to-peer communication link called the SCmessage bus. The primary purpose of the SCbus is to support the exchange of real time telephonic voice, facsimile, data, video and other media streams. The purpose of the SCmessage bus is to transport interprocess control and status messages. This specification defines only the physical and data link OSI layers of the four layer transport facility.||ANSI Stabilized|
|ANSI/VITA 6.1-1996 (S2011)||SCSA Extensions||This standard provides feature extensions to the ANSI/VITA 6.0 standard.||ANSI Stabilized|
|VITA 10-1995 (R2002)||SKYchannel Packet Bus on VME||This standard describes a high performance SKYchannel Packet Bus architecture that is fully compatible with the VMEbus standards. This standard addresses communication between VME boards using the P2 connector. This includes the physical layer for communication between the VME board and a SKYchannel Backplane through VME P2/J2, and the data link layer for communication from board to board.||ANSI Withdrawn|
|ANSI/VITA 12-1997 (S2012)||M-Module||This standard defines minimum mechanical and electrical characteristics of M-Modules, a method of implementing modular circuit boards with specific functions that can be used to add functionality to other larger printed circuit boards.
|ANSI/VITA 17-1998 (S2011)||Front Panel Data Port (FPDP)||This standard defines a point to point data interconnect for use on front panel Eurocard modules. FPDP consists of a multi-drop synchronous parallel non-addressable bus link between multiple boards in a single chassis. The link is made to a connector on the front panel of each board by means of an eighty conductor ribbon cable. The purpose of this standard is to allow products to be designed to work with other FPDP products. The degree of interoperability may depend on the layers of functionality above the physical and data link layers. These higher layers are not part of this standard.||ANSI Stabilized|
|ANSI/VITA 17.1-2015||Serial Front Panel Data Port (sFPDP)||Serial FPDP (sFPDP) is directly related to the FPDP standard, deriving its serial protocol from the defined protocol and control signals of FPDP. The Serial FPDP standard supports seven link speeds: 1.0625, 2.125, 2.5, 4.25, 5.0, 8.5, and 10.0 Gbaud. These seven link speeds can support data transfer rates in excess of 105 MBps, 210 MBps, 247 MBps, 420 MBps, 494 MBps, 840 MBps, and 988 MBps respectively. Included in this definition are the data frame structure, the link layer protocol, and the physical media requirements.||ANSI Ratified|
|VITA 17.2||Serial Front Panel Data Port (sFPDP) Channel Bonded Protocol||The main objective of VITA 17.2 is to increase the bandwidth of the link. This can be done by both increasing the speed of the link, and by providing the ability to channel bond several lanes together.
The VITA 17.2 protocol is designed to provide functional compatibility with both VITA 17 and VITA 17.1 protocols, while providing increased bandwidth. In addition, the VITA 17.2 protocol is designed to provide a minimum footprint, and to maximize the use of dedicated hardware that is found in current FPGAs.
|Working Group - Draft|
|ANSI/VITA 17.3-2018||Serial Front Panel Data Port (sFPDP) Gen 3.0||This standard defines VITA 17.3 “Serial FPDP Gen 3.0” (sFPDP), a high-speed serial communications interface. Included in this definition are various user data framing methods, supported system configurations, and the Link Layer Protocol.||ANSI Ratified|
|ANSI/VITA 20-2005 (S2018)||Conduction Cooled PMC||This standard defines the methodology and implementation details to allow the creation of conduction cooled PMC modules to ensure electrical and physical compatibility with various host card modules onto which conduction cooled PMCs are mounted.
|ANSI/VITA 23-1998 (S2011)||VME64 Extensions for Physics and Other Applications||This standard defines a series of recommended practices for the use of VMEbus in the physics community. This standard is generally consistent with the NIM/VME-P document 9612, "VMEbus for Physics Applications", that has served as a working group approach, and has also utilized items from the CERN VSC "Recommended Practices" document.||ANSI Stabilized|
|ANSI/VITA 26-1998 (S2011)||Myrinet on VME Protocol||This standard describes the inter-computer, Myrinet packet network that is fully compatible with existing VMEbus standards and their extensions. This standard addresses communication between VME boards using interconnect either on the front panel or on the backplane. The communication may use cables or an overlay (such as a backplane). The standard defines the interface between a VME board and Myrinet, allowing not only intra-subrack, board-to-board communication, but also a uniform extension for inter-subrack, inter-cabinet, and even local-area-network (LAN) communication. This standard includes, either directly or by reference, the specification of the Data Link level, timing information, character set, signals, and the details of the connectors.||ANSI Stabilized|
|VITA 29.0-2001||PC*MIP||Defines the mechanical form factor and the pin assignments for a small form factor mezzanine module based on the PCI bus.||ANSI Withdrawn|
|ANSI/VITA 30-2000 (S2011)||2mm Connector Practice for Eurocard Systems||Defines an equipment practice based on a combination of 2 mm connectors, per IEC 61076-4-101, and subracks, racks and printed boards based on the Euroboard form factors.
In the late 1980's, the VME specification expanded for 64 bit data and address capability, which also affected the specified connectors used at the plug-in module interface. The designers utilized IEC 61076-4-101 2 mm based connectors to increase connector pin counts and to facilitate the adoption of certain architectural features and capabilities. Physical features required to incorporate these connectors into the IEEE 1101.1 and IEC 60603-2 based architecture were detailed in the individual specifications. This document provides a means to specify this information without including extensive details in the systems specifications. The combination of Euroboard form factors and 2 mm connectors has been utilized in other system architectures and is anticipated to be included in future systems. This specification defines a variety of configurations that combine Euroboards and 2 mm connectors in a manner that facilitates references to such architecture in such current and future applications.
|ANSI/VITA 30.1-2008 (R2014)||2mm Connector Practice for Conduction Cooled Euroboards||This standard is intended to be a companion specification to other standards as referenced. Other uses for this specification are in no way prohibited. The aim is to ensure mechanical interchangeability of conduction-cooled circuit card assemblies in a format suitable for military and rugged applications and to ensure their compatibility with both conduction cooled chassis and commercial, air-cooled, single height (3U) and double-height (6U) x 160mm, Euroboard chassis.||ANSI Ratified|
|VITA 30.2-2001 (IEC)||Power Connector Equipment Practice||Describes various separable connectors that can be used to conduct electrical current between two printed boards. Typical applications include power supplies or other power management devices. It has been developed to aid in the design of equipment where such connectors are typically found. The information included consists of interface and profile dimensions, printed board layout dimensions, suggested or actual signal and power pin assignments as well as information regarding standards that may exist for the connectors. No consideration is given to current carrying capacities of the connector systems nor to the optimization or validity of any pin assignment schemes, which may be included. Similarly, if connector locations are given relative to common industry board practices, they are not to be assumed to be the sole possible location of such connectors. Power connectors are defined, for the purpose of this standard, as separable connectors that are designed to provide current to devices at levels consistent with the overall operating power of the device. As such, they must have at least one (1) contact capable of carrying five (5) amps or more of electrical current.||Industry Technical Agreement|
|ANSI/VITA 31.1-2003 (S2014)||Gigabit Ethernet on VME64x Backplanes||This standard leverages the PICMG 2.16 packet Switched backplane specification that adds a switched network based on Gigabit Ethernet to CompactPCI backplanes. The PICMG 2.16 CompactPCI P3 connector has two Gigabit Ethernet ports for improved performance and redundancy. The CompactPCI P3 connector and the VME64x P0 connector are identical IEC 61076-4-101 2 mm based connectors and have the same placement on the backplane. This standard adopts the PICMG 2.16 P3 connector pin assignment for use on VME64x boards. This standard also adopts the definition of the fabric card described in PICMG 2.16. PICMG 2.16 compliant systems and VITA 31.1 systems can use the same switched fabric boards.||ANSI Stabilized|
|ANSI/VITA 32-2003 (S2014)||Processor PMC||The complete physical (mechanical) and the environmental layers are retained as specified in the IEEE 1386 CMC ("Common Mezzanine Card") standard except as noted in this document. If the information in this document contradicts IEEE 1386 or IEEE 1386.1, this document takes precedence.
Processor PMC cards are used where modular attachment of a processor is desired. These processor PMC cards may be used in conjunction with PMC I/O cards, traditional PCI cards, or with directly attached PCI components. As such, Processor PMCs increase the modularity of a computer system and thus complement, rather than compete with, the existing family of PMC cards.
Processor PMC cards are expected to electrically operate with existing carrier boards (or motherboards); that is, while the carrier may be redesigned to take advantage of the enhanced functions that are offered by this standard, such a redesign should not be a requirement to insure proper operation. Indeed, Processor PMCs shall be specifically enabled to operate as master/host CPUs; otherwise, such cards revert to traditional PMC modes, operating as intelligent slave/target processor boards.when that support is required within PMC and Processor PMC designs.
|ANSI/VITA 35-2000 (S2011)||PMC-P4 Pin Out Mapping to VME P0 and VME64x P2||This standard provides pin mapping assignments between a PCI mezzanine Card (PMC) module's user IO connector (P4) and the VME host's user IO connector. Four mappings are provided.
Other standards such as Compact PCI (CPCI) which supports a PMC and a VME-P0 style connector on the host could also use this standard.
|VITA 36-199x||PMC I/O Module||This proposed standard defines a module intended to pair with a CMC compliant card via the 64 I/O signals defined on the Pn4/Jn4 connectors.||Working Group - Draft - Withdrawn|
|ANSI/VITA 38-2003 (S2013)||System Management on VME||This standard is based on the PICMG 2.9 System Management specification and describes the additional requirements for implementing Intelligent Platform Management Interface (IPMI) in a VME system. IPMI describes a hardware independent interface between chassis sensors and the operating system. IPMI is particularly useful for managing servers and High Availability systems.||ANSI Stabilized|
|ANSI/VITA 39-2003 (S2014)||PCI-X for PMC and Processor PMC||PCI-X is defined in the PCI-X Addendum to the PCI Local Bus Specification and is the basis for the updates in this document.The physical (mechanical) and the environmental layers are specified in the IEEE 1386 CMC ("Common Mezzanine Card") and IEEE 1386.1 PMC ("PCI Mezzanine Card"). VITA 32 Processor PMC standard incorporates a set of extensions to IEEE 1386/1386.1 creating a new class of CPU based PMC cards.||ANSI Stabilized|
|VITA 40-2003||Service and Status Indicator Standard||The purpose of this standard is to provide the information needed to design service indicators for boards, subsystems, and enclosures.
This document describes a service indicator standard that seeks to be as compatible as possible with existing indicator standards and their extensions across different product markets. This standard addresses the meaning and application of specific colors to service indicators. This standard also defines and assigns meanings to specific approved behaviors or states for each color. It specifies where indicators must be placed and in what order, and it specifies luminance levels and viewing angles.
|ANSI/VITA 41.0-2006 (S2018)||VXS: VMEbus Switched Serial Standard||The VME Switched Serial (VXS) standards comprises this base standard defining physical features of VXS components, coupled with a set of protocol layer standards to define the specific serial interconnect used in a system implementation.
The VXS base standard defines physical features that enable high-speed communication in a VME compatible system. These features include: addition of a high speed connector to the VME64x board in the P0/J0 position, a 6U by 160mm by 6HP Eurocard format board with many high speed connectors which may act as a switch, and the backplane/chassis infrastructure needed to support these features. In addition to defining a high -speed connector in the P0/J0 area, VXS also defines alignment and keying features which may be used to protect this and future alternate connectors.
The ratio of one high-speed connector per payload board to many on the switch card lends itself to a star topology where each payload card is connected to a central switch. For higher reliability and/or load balancing, two switch cards may be used in a dual star configuration. Interswitch links may be included for reliability and load balancing reasons as well. Although this topology is not required it is a natural fit for the system features.
|ANSI/VITA 41.1-2006 (RS018)||VXS: 4x InfiniBand Protocol Layer||The objectives of this document are:
- To assign 4X InfiniBand signals for communication over the data links defined in VITA 41.0 (the base VXS specification).
- To provide requirements, constraints and recommendations for the use of the InfiniBand data links.
- To provide requirements, constraints and recommendations for the use of InfiniBand in-band management.
- To provide requirements, constraints and recommendations for the use of I2C out-of- band management.
The requirements and design rules defined in this specification are intended to be consistent with the applicable sections of the InfiniBand Specification. It is expected that VXS.1 products will comply with InfiniBand Signal, Link, Transport, and Management layers in order to maximize interoperability with other InfiniBand hardware and software products.
|ANSI/VITA 41.2-2006 (S2018)||VXS: 4x Serial RapidIO Protocol Layer||The objectives of this document are:
- To assign 4X Serial RapidIO signals for communication over the data links defined in VXS.0.
- To provide guidelines for the use of the Serial RapidIO data links.
- To provide guidelines for the use of Serial RapidIO in-band management. Out-of-band management.
- To provide guidelines for the use of I2C
The guidelines and design rules defined in this specification are intended to be consistent with the applicable sections of the Serial RapidIO Specification. It is expected that VXS.2 products will comply with Serial RapidIO Signal, Link, Transport, and Management layers in order to maximize interoperability with other Serial RapidIO hardware and software products.
|ANSI/VITA 41.6-2009 (R2016)||VXS: 1x Gigabit Ethernet Control Channel Layer||The objectives of this document are:
- To define and assign 1X GigE signals for communication over signal sets currently defined as reserved for future use in VXS.0.
- To provide guidelines for the use of the GigE data links.
- To provide guidelines for the use of GigE System management.
- To provide guidelines for the use of GigE switching services and management.
The guidelines and design rules defined in this specification are intended to be consistent with the applicable sections of the IEEE 802.3 Specification.
|ANSI/VITA 42.0-2016||XMC: Switched Mezzanine Card Base Specification||Specific goals include supporting:
- A high-speed switched interconnect.
- Open, standardized technologies for switched fabrics.
- Standard PMC form factors and stacking heights.
- Compatibility with existing PMC specifications.
- PMC, XMC, or dual-mode mezzanine cards and carriers.
- Standard VME, CompactPCI, Advanced TCA, and PCI Express carrier.
- Optional conduction cooling.
In support of these goals, this document specifies the mechanical and generic electrical requirements necessary to serve as a basis for any number of protocol layer standards built on and complying with this standard.
|ANSI/VITA 42.1-2006 (S2018)||XMC: Parallel RapidIO Protocol Layer||This standard defines an open standard for supporting Parallel RapidIO switched interconnect protocol on the XMC form factor. The objectives of this document are:
- To assign Parallel RapidIO signals for communication over the high-speed connectors and data links defined in XMC.0.
- To provide guidelines for the use of the Parallel RapidIO data signals.
The guidelines and design rules defined in this standard are intended to be consistent with the applicable sections of the Parallel RapidIO Specification. It is expected that XMC.1 products will comply with Parallel RapidIO Physical, Transport, and Logical layers in order to maximize interoperability with other Parallel RapidIO hardware and software products.
|ANSI/VITA 42.2-2006 (S2018)||XMC: Serial RapidIO Protocol Layer||This specification defines an open standard for supporting the Serial RapidIO switched interconnect protocol on the XMC form factor. In light of this objective, specific goals include supporting:
- To assign 4X Serial RapidIO signals for communication over the switch connectors defined in XMC.0.
- To provide guidelines for the use of Serial RapidIO signals.
The guidelines and design rules defined in this standard are intended to be consistent with the applicable sections of the Serial RapidIO specification. It is expected that XMC.2 products will comply with Serial RapidIO Physical, Transport, and Logical layers to realize maximum interoperability with other Serial RapidIO hardware and software.
|ANSI/VITA 42.3-2014||XMC: PCI Express Protocol Layer||This standard defines an open standard for supporting PCI Express switched interconnect protocol on the XMC form factor. The objectives of this document are:
- To assign 1, 2, 4, 8, 16 and 32 Lane PCI Express interfaces, or Links for communication over the switch connectors defined in XMC.0.
- To provide guidelines for the use of PCI Express signals.
|ANSI/VITA 42.6-2009 (R2015)||XMC: 10 GbE 4-Lane Protocol Layer||This standard defines a standard for supporting 10 Gigabit Ethernet using XAUI switched interconnect protocol on the XMC form factor by the assignment of XAUI signals and by the provision of guidelines for the use of XAUI signals.
Products should comply with XAUI Physical, Transport, and Logical layers to ensure interoperability.
|ANSI/VITA 46.0-2019||VPX: Baseline||
Commonly known as VPX, this family of standards defines entirely high-speed connectors in part to carry mappings for popular switched serial fabrics including Gigabit Ethernet, PCI Express, Serial RapidIO, InfiniBand, and Aurora. It also defines an increased power envelope including a 48V profile, and additional cooling methods.
The VITA 46 base standard defines physical features that enable high-speed communication in a compliant system. These features include: a 6U by 160mm by 4HP pitch Eurocard format board with high speed differential connectors, a 6U by 160mm by 4HP pitch Eurocard format board with a combination of high speed differential and single-ended connectors, and the backplane/chassis infrastructure needed to support these features. The base standard also defines similar physical features for 3U by 160mm by 4HP pitch Eurocard format, providing the same two types of connector options discussed above for 6U plug-in modules. Many features called for in the base specification will be compatible with the requirements of other standards, such as VITA-48, but this standard concerns only the IEEE 1101 compatible applications.
This base standard also defines alignment and keying features used to protect the connector system.
|ANSI/VITA 46.1-2007 (S2018)||VPX: VMEbus Signal Mapping||This standard supplements the VITA 46 base specification with the definition for the VMEbus signals as mapped to a VITA 46 connector.||ANSI Stabilized|
|ANSI/VITA 46.3-2012 (R2018)||VPX: 4x Serial RapidIO Signal Mapping||This standard supplements the VITA 46 base specification with the definition for the 4x Serial RapidIO signals as mapped to a VITA 46 connector.||ANSI Ratified|
|ANSI/VITA 46.4-2012 (R2018)||VPX: PCI Express Signal Mapping||This standard supplements the VITA 46 base specification with the definition for the PCI Express signals as mapped to a VITA 46 connector.||ANSI Ratified|
|ANSI/VITA 46.6-2013 (R2018)||VPX: Gbit Ethernet Control Plane Signal Mapping||This standard supplements the VITA 46 base specification with the definition for the Gbit Ethernet signals as mapped to a VITA 46 connector.||ANSI Ratified|
|ANSI/VITA 46.7-2012 (R2018)||VPX: 10Gbit Ethernet Signal Mapping||This standard supplements the VITA 46 base specification with the definition for the 10 Gbit Ethernet signals as mapped to a VITA 46 connector.||ANSI Ratified|
|VITA 46.8||VPX: InfiniBand||This standard supplements the VITA 46 base specification with the definition for the InfiniBand signals as mapped to a VITA 46 connector.||VITA Withdrawn|
|ANSI/VITA 46.9-2018||VPX: PMC/XMC Rear I/O Fabric Signal Mapping on 3U and 6U VPX Modules||The objective of this standard is to detail the connection mapping between the defined mezzanine connector contact position and the associated backplane (BP) connector contact position for the detailed combinations:
- 3U/6U VITA 46 carrier with PMC JN4 I/O mapping to backplane P2
- 3U/6U VITA 46 carrier with XMC JN6 I/O mapping to backplane P2
- 6U VITA 46 carrier with PMC JN4 I/O mapping to backplane P3 and P6
|ANSI/VITA 46.10-2009 (R2015)||VPX: Rear Transition Module||The objectives of this standard are:
- Define 6U by 80mm and 3U by 80mm Eurocard format rear transition modules suitable for air-cooled, ruggedized use;
- Define a suitable high-speed connector family for use in these plug-in modules;
- Make provision for power connections and I/O connections for the rear transition module.
|ANSI/VITA 46.11-2015||VPX: System Management||
This document defines a system management architecture for VPX systems.
|ANSI/VITA 47-2007||Environments, Design and Construction, Safety, and Quality for Plug-In Units||COTS plug-in units are widely used in commercial and military, ground and aerospace, mobile applications. Certification of COTS plug-in units, by supplying vendors, to this standard will facilitate the cost effective integration of these items in larger systems.||ANSI Ratified|
|VITA 47.1||Environments, Design and Construction, Safety, and Quality for Plug-In Units||This standard defines the common Environments, Design and Construction, Safety, and Quality for Plug-In Module requirements common across VITA 47.1, VITA 47.2, and VITA 47.3. VITA 47.2 and VITA47.3 will contain the unique requirements aligned with the definitions of IPC J-STD-001. Class 2 and 3 respectfully.||Working Group - Draft|
|VITA 47.2||Environments, Design and Construction, Safety, and Quality for Plug-In Units||This standard defines the unique Environments, Design and Construction, Safety, and Quality for Plug-In Module requirements related to products meant to align with the applications defined in IPC J-STD-001, Class 2. The common requirements applicable to products meant to align with the definitions of IPC J-STD-001 Class 2 and 3 will be in VITA 47.1.||Working Group - Draft|
|VITA 47.3||Environments, Design and Construction, Safety, and Quality for Plug-In Units||This standard defines the unique Environments, Design and Construction, Safety, and Quality for Plug-In Module requirements related to products meant to align with the applications defined in IPC J-STD-001, Class 3. The common requirements applicable to products meant to align with the definitions of IPC J-STD-001 Class 2 and 3 will be in VITA 47.1.||Working Group - Draft|
|ANSI/VITA 48.0-2010||VPX REDI: Ruggedized Enhanced Design Implementation Mechanical Base Specification||This standard provides an overview of the associated plug-in units for air-cooling, conduction cooling, and liquid flow thru and spray cooling applications. Specific connector-mounting details are defined in VITA 46. The VITA 48 family of standards will define applicable detailed dimensions of key module and sub-rack interfaces. The implementations described in this standard are targeted for 3U and 6U form factor boards on 0.85 and 1.00 centers. However, the packaging approach presented is applicable to boards with other form factors, different connector series and can accommodate alternate module pitches.
The purpose of this standard is to define an overall approach to packaging modules to improve both their thermal and structural characteristics as well as incorporate the provisions for 2 level maintenance. In addition this standard will define the applicable environmental requirements of plug-in units to ensure successful integration into higher levels of assembly.
|ANSI/VITA 48.1-2010||VPX REDI: Mechanical Specifications for Microcomputers Using Air Cooling Applied to VPX||This standard defines the dimensions of associated plug-in units for air-cooling applications and connector-mounting details together with applicable detail dimensions of key sub-rack interfaces. The module assemblies defined by this standard will be compatible with two level maintenance applications.||ANSI Ratified|
|ANSI/VITA 48.2-2010||VPX REDI: Mechanical Specifications for Microcomputers Using Conduction Cooling Applied to VPX||This standard defines the dimensions of associated plug-in units for conduction cooling applications and connector-mounting details together with applicable detail dimensions of key sub-rack interfaces. The module assemblies defined by this standard will be compatible with two level maintenance applications.||ANSI Ratified|
|VITA 48.3||VPX REDI: Mechanical Specification Using Liquid Cooling Applied to VPX, Manifold Below the Backplane||This standard defines the dimensions of associated plug-in units for liquid cooling applications and connector-mounting details together with applicable detail dimensions of key sub-rack interfaces. The module assemblies defined by this standard will be compatible with two level maintenance applications.||Working Group - Draft|
|ANSI/VITA 48.4-2018||VPX REDI: Mechanical Specification Using Liquid Flow Thru Applied to VPX||This standard establishes the mechanical design requirements for a LFT cooled electronic VPX module.||ANSI Ratified|
|ANSI/VITA 48.5-2010 (R2017)||VPX REDI: Mechanical Specification Using Air Flow-through Cooling Applied to VPX||This standard establishes the design requirements for an air-flow-through cooled plug-in unit with a 6U form factor.||ANSI Ratified|
|ANSI/VITA 48.7-2014||VPX REDI: Mechanical Specification Using Air Flow-By Cooling Applied to VPX||This standard establishes the design requirements for an Air Flow-By cooled plug-in unit with a 6U form factor.||ANSI Ratified|
|ANSI/VITA 48.8-2017||VPX REDI: Mechanical Specification Using Air Flow-By Cooling Applied to VPX||This standard establishes the design requirements for an air-flow-through cooled plug-in unit with a 6U form factor.||ANSI Ratified|
|ANSI/VITA 49.0-2015||VITA Radio Transport (VRT)||This standard defines a transport-layer protocol designed to promote interoperability between RF (radio frequency) receivers and signal processing equipment in a wide range of applications.||ANSI Ratified|
|ANSI/VITA 49.1-2015||VITA Radio Link Layer (VRL)||This standard specifies an optional encapsulation protocol for VITA-49.0 (VRT) packets.||ANSI Ratified|
|ANSI/VITA 49.2-2017||VITA Radio Transport (VRT) Electromagnetic Spectrum: Signals
|This standard specifies rules for control packets.||ANSI Ratified|
|ANSI/VITA 49A-2015||Spectrum Survey Interoperability||This document specifies an interoperability standard that is applicable to spectrum-survey applications. It is intended to foster high-throughput and adaptable processing in a large-scale environment. It specifically considers the needs of devices based around 32-/64-bit general-purpose processors (GPP) and FPGAs that utilize Internet Protocol (IP) as the underlying transport between processing devices.||ANSI Ratified|
|ANSI/VITA 51.0-2012 (R2018)||Reliability Prediction||This document provides an electronics failure rate prediction standard, and establishes a Community of Practice. It addresses the limitations of existing prediction practices with a series of subsidiary specifications that contain the "best practices" within industry for performing electronics failure rate predictions. The development of ANSI/VITA 51.0 and the subsidiary specifications is an effort to give the mean time between failure (MTBF) calculations consistency and repeatability.||ANSI Ratified|
|ANSI/VITA 51.1-2013 R2018)||Reliability Prediction: MIL-HDBK-217 Subsidiary Standard||This standard provides standard defaults and methods to adjust the models in MIL-HDBK-217F Notice 2. This is not a revision of MIL-HDBK-217F Notice 2 but a standardization of the inputs to the MIL-HDBK-217F Notice 2 calculations to give more consistent results.||ANSI Ratified|
|ANSI/VITA 51.2-2016||Physics of Failure Reliability Predictions||This standard includes a discussion of the philosophy, context for use, definitions, models for key failure mechanisms, definition of the input data required, default values if technically feasible or the typical range of values as a guideline. It defines how modeling results are interpreted and used. It requires the documentation of modeling inputs, assumptions made during the analysis, modifications to the models and rationale for the analysis.||ANSI Ratified|
|ANSI/VITA 51.3-2010 (R2016)||Qualification and Environmental Stress Screening in Support of Reliability Predictions||This standard provides rules, permissions, and observations to assure that cost effective Qualification and Environmental Stress Screening support valid reliability predictions and enhance electronics reliability. It includes a discussion of the systems engineering relationships between Qualification, Environmental Stress Screening, and reliability.||ANSI Ratified|
|ANSI/VITA 53.0-2010 (R2017)||Standard for Commercial Technology Market Surveillance||Technology refresh events are fueling the large majority of new DoD acquisition efforts in the post-"Perry memo" era of increased DoD reliance on commercial technology vendor design, production, support, and repair services. Preferred DMSMS management method for DoD programs.||ANSI Ratified|
|ANSI/VITA 57.1-2019||FMC: FPGA Mezzanine Cards Base Standard||This standard describes an IO mezzanine module, which shall connect to, but is not limited to, 3U and 6U form factor cards. This mezzanine module is in a smaller form factor, when compared to PMC/XMC modules and assumes that it will be connected to a FPGA device or other device with reconfigurable IO capability. This standard describes FMC IO modules and introduces an electro-mechanical standard that creates a low overhead bridge. This is between the front panel IO, on the mezzanine module, and an FPGA processing device on the carrier card, which accepts the mezzanine module.||ANSI Ratified|
|VITA 57.2||FMC: Metadata Description||XML metadata descriptions for FMC.||Working Group - Draft|
|ANSI/VITA 57.4-2018||FMC: FPGA Mezzanine Cards Base Standard - Next Generation||This standard extends the VITA 57.1 FMC standard by specifying two new connectors that enable additional Gigabit Transceiver interfaces that run at up to 28Gbps. It also describes FMC+ IO modules which support this enhanced version of the FMC electro-mechanical standard. This is between the front panel IO, on the mezzanine module, and an FPGA processing device on the carrier card, which accepts the mezzanine module. Additional signals to support backplane reference clock and synchronization have been added. The VITA 57.4 specification is backwards compatible in that a VITA 57.4 carrier card can still support a VITA 57.1 FMC.||ANSI Ratified|
|VITA 57.5||Development Tools for FMC+||The goal of this project is to develop a set of tools for FMC and FMC+ designs.||Study Group|
|ANSI/VITA 58.0-2009 (R2014)||Line Replaceable Integrated Electronics Chassis||This standard provides common design and performance requirements for a family of integrated electronic chassis incorporating updated industry standard high speed electronic assemblies and designed for rugged environments.||ANSI Ratified|
|ANSI/VITA 58.1-2013||Line Replaceable Integrated Electronics Chassis, Liquid Cooled||This standard identifies the particular requirements for a liquid cooled chassis configuration conforming to the ANSI/VITA 58.0 base specification.||ANSI Ratified|
|VITA 59.0||Rugged COM Express™||This standard VITA 59.0, Rugged System-On-Module Express RSE, describes an innovative step forward for the provision of high-speed serial interconnects for computer modules and makes such modules usable in harsh-environment applications.||Working Group - Draft|
|ANSI/VITA 60-2012 (R2018)||VPX: Alternative Connector for VPX||This standard describes VITA 60.0 Alternate Connector for VPX for VMEbus systems VITA 60.0 provides an alternative connector to the one specified in VITA 46.0, VPX Baseline Standard. Because the 46.0 and the 60.0 connectors are not intermateable a VITA 60.0 module will not plug into a VITA 46.0 backplane and vice versa. However, the VITA 60.0 draft standard provides VPX users with the flexibility to choose a VPX module and backplane connector combination for their specific application requirements.||ANSI Ratified|
|ANSI/VITA 61.0-2014||XMC 2.0||This standard, based upon VITA 42.0 XMC, defines an open standard for supporting high-speed, switched interconnect protocols on an existing, widely deployed form factor, but utilizing an alternate, ruggedized, high speed mezzanine interconnector known as VITA 61 XMC 2.0.||ANSI Ratified|
|ANSI/VITA 62-2016||VPX: Modular Power Supply||Defines the power generation requirements for a module that can be used to power systems that support a VITA 62 slot on the VPX backplane. VITA 62 uses the standard VPX 3U/6U form factor and complies to the requirements defined in VITA 48.0. VITA 62 has utility functionality that includes N+1 failover, VBAT and 50ms holdup. VITA 62 defines a set of connectors that mate with a VITA 62 compatible backplane such that VITA 62 module can be plugged into the backplane.||ANSI Ratified|
|VITA 62.1||Power Supply Front-end for High-voltage/3-phase 3U Module||This standard provides requirements for building a high-voltage/3-phase/3U class front-end power supply module that can be used to power a VPX chassis in the VITA 62 family of standards. The module will fit within the standard envelope defined for VPX modules in the VITA 48.0 standards.||Working Group|
|ANSI/VITA 63-2015||VPX: KVPX Alternate Connector||This document describes an open standard for VITA 63.0 Hyperboloid Alternative Connector for VPX. This standard provides an alternative connector to the one specified in the VITA 46.0 VPX Baseline Standard. Because the 46.0 and the 63.0 connectors are not intermateable, a VITA 63.0 module will not plug into a VITA 46.0 backplane and vice versa. However, the VITA 63.0 draft standard provides VPX users with the flexibility to choose a VPX module and backplane connector combination for their specific application requirements.||ANSI Ratified|
|ANSI/VITA 65-2017||OpenVPX System||The OpenVPX System standard was created to bring versatile system architectural solutions to the VPX market. Based on the extremely flexible VPX family of standards, the OpenVPX standard uses module mechanical, connectors, thermal, communications protocols, utility, and power definitions provided by specific VPX standards and then describes a series of standard profiles that define slots, backplanes, modules, and standard development chassis.||ANSI Ratified|
|ANSI/VITA 65.1-2017||OpenVPX Profile Tables||This standard documents variations of Slot, Backplane, and Modules Profiles. As part of the Slot Profile Description, there are also some Connector Modules defined. This document is primarily tables which are referenced by [VITA 65.0].||ANSI Ratified|
|ANSI/VITA 66.0-2016||VPX: Optical Interconnect On VPX - Base Standard||This standard defines a family of blind mate Fiber Optic interconnects for use with VITA 46 backplanes and plug-in modules.||ANSI Ratified|
|ANSI/VITA 66.1-2012||VPX: Optical Interconnect On VPX - MT Variant||MT Mechanical Mating I/F Definition
MT Optical Mating I/F Definition
|ANSI/VITA 66.2-2013 (R2018)||VPX: Optical Interconnect On VPX - ARINC 801||ARINC 801 Mechanical Mating I/F Definition
ARINC 801 Optical Mating I/F Definition
|ANSI/VITA 66.3-2012 (R2018)||VPX: Optical Interconnect On VPX - Expanded-Beam||Expanded Beam Mechanical Mating I/F Definition
Expanded Beam Optical Mating I/F Definition
|ANSI/VITA 66.4-2016||VPX: Optical Interconnect On VPX - Half Width MT Variant||Half Width Optical Interconnect||ANSI Ratified|
|VITA 66.5||VPX: Optical Interconnect, Spring-Loaded Contact on Backplane||Working Group - Draft|
|ANSI/VITA 67.0-2012||VPX: Coaxial Interconnect - Base Standard||This standard establishes a structure for implementing blind mate analog coaxial interconnects with VPX backplanes and plug-in modules, and to define a specific family of interconnects and configurations within that structure.||ANSI Ratified|
|ANSI/VITA 67.1-2012||VPX: Coaxial Interconnect, 3U, 4 Position SMPM Configuration||This standard details the configuration and interconnect within the structure of VITA 67.0 enabling a 3U VITA 46 interface containing multi-position blind mate analog connectors with up to 4 SMPM contacts.||ANSI Ratified|
|ANSI/VITA 67.2-2012||VPX: Coaxial Interconnect, 6U, 8 Position SMPM Configuration||This standard details the configuration and interconnect within the structure of VITA 67.0 enabling a 6U VITA 46 interface containing multi-position blind mate analog connectors with up to 8 SMPM contacts.||ANSI Ratified|
|ANSI/VITA 67.3-2017||VPX: Coaxial Interconnect, 6U, 4 Position SMPM Configuration||This standard details the configuration and interconnect within the structure of VITA 67.0 enabling a 6U VITA 46 interface containing multi-position blind mate analog connectors with up to 4 SMPM contacts.||ANSI Ratified|
|ANSI/VITA 68.0-2017||VPX: Compliance Channel||This standard defines a VPX compliance channel including common backplane performance criteria required to support multiple fabric types across a range of defined baud rates.||ANSI Ratified|
|ANSI/VITA 68.1-2017||VPX: Fixed signal integrity budget||This standard defines a fixed signal integrity budget for a VPX compliance channel.||ANSI Ratified|
|VITA 69.0||Common Glossary||Glossary of technical terms commonly used in VITA standards. This project was transferred to VITA 85.2 VSO Glossary Study Group.|
|VITA 70.0||Common Standard Template||Standard formats to be used for VITA standards. VITA Member use only.|
|VITA 73.0-2012||Small Form Factor||Provides a standard mechanical format for standardization of switched serial interconnects for small form-factor applications, with specific concern taken to allow deployment in ruggedized environments.||VITA Withdrawn|
|ANSI/VITA 74.0-2017||VNX Small Form Factor||Provides a standard mechanical format for standardization of switched serial interconnects for small form-factor applications, with specific concern taken to allow deployment in ruggedized environments.||ANSI Ratified|
|VITA 75.0-2012 VDSTU||Rugged Small Form Factor - Base Standard||This standard for a rugged small form factor describes overall subsystem attributes such as the envelope of the subsystem (box) and the organization of the dot specifications.||VITA Draft Standard for Trial Use|
|VITA 75.11-2012 VDSTU||Rugged Small Form Factor - Subsystem I/O Interfaces||This standard for a rugged small form factor describes the standardization of front panels, connectors, I/O signal pin assignments, and power for VITA 75 subsystems.||VITA Draft Standard for Trial Use|
|VITA 75.20-2012 VDSTU||Rugged Small Form Factor - Cooled via Free Air Convection||This standard for a rugged small form factor describes the standardization of mounting and cooling for free air convection cooled VITA 75 subsystems.||VITA Draft Standard for Trial Use|
|VITA 75.22-2012 VDSTU||Rugged Small Form Factor - Cooled via Conduction to Cold Plate||This draft standard for a rugged small form factor describes the standardization of mounting and cooling for conduction to a cold plate cooled VITA 75 subsystem.||VITA Draft Standard for Trial Use|
|ANSI/VITA 76.0-2016||High Performance Cable - Ruggedized 10 Gbaud Bulkhead Connector for Cu and AOC Cables||This standard defines a rugged standardized 10 Gbaud interconnect system with high pin count and high density for I/O. It is capable of supporting multiple protocols and power while being interoperable with both Copper Cabling and Active Optic Cabling.||ANSI Ratified|
|ANSI/VITA 78-2015||SpaceVPX Systems||
This document describes an open standard for creating high performance fault tolerant interoperable backplanes and modules to assemble electronic systems for spacecraft and other high reliability (availability) applications. Such systems will support a wide variety of use cases across the aerospace community that includes non-spacecraft systems. This standard leverages the VPX standards family and the commercial infrastructure that supports these standards in non-space applications.
|VITA 79||Embedded Photonics||
Develop a standard based on work done by the JEDEC 13.6 subcommittee.
|Working Group - Draft|
|VITA 80||Interoperability||Develop a method for testing interoperability among VPX modules.||Working Group - Draft|
|VITA 85.2||Common Glossary||Glossary of technical terms commonly used in VITA standards (to be used by draft editors in creating VITA standards, not available to non-VITA members).||VITA Members Only|
|ANSI/VITA 86-2019||High Voltage Input Sealed Connector Power Supply||This standard defines an environmentally sealed connector pair which is compatible with only the backplane footprint as defined in VITA 62.0 for 3U power supplies operating in harsh environments operating off of a high voltage input.||ANSI Ratified|